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Participant leoeltipo
Participant
174 Views
Registered: ‎12-11-2017

IP With block design and microblaze

Hello,

I want to do something that should be simple, but apparently it is not. I want to create a new IP. That new IP is created in a new project, using a block design as it eases connecting stuff. My IP also includes a microblaze processor.

I package my IP but, when I instantiate it in another project, the synthesis and implementation go well, but the processor is not in the address map. If I export the hardware, the processor does not show up in Xilinx SDK. Is there any way to package a custom IP with a microblaze, and expose the processor to the top level design that instantiates it?

By the way, Xilinx folks should find a better way of creating and easily editing IPs that contain block designs. I could not find the way to do this clean, and I always have to keep a vivado project just for editing the IP.

Thanks,

Leo

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2 Replies
Xilinx Employee
Xilinx Employee
98 Views
Registered: ‎10-30-2017

Re: IP With block design and microblaze

Hi @leoeltipo ,

We already have published an AR to package the Microblaze in BD and using it in another project. Please refer this AR: https://www.xilinx.com/support/answers/67083.html

Best Regards,
Srikanth
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Participant leoeltipo
Participant
73 Views
Registered: ‎12-11-2017

Re: IP With block design and microblaze

Hi @savula ,

 

Thanks for the repply seems very interesting. However, I do not want to add the ELF file. I want the Microblaze to be discovered at the top level design. I could do this, but when I export the hardware, the microblaze in the IP does not get recognized by SDK so I cannot program it. Is there a way around it?

 

Thanks again,

Leo

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