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Visitor nliang
Registered: ‎05-30-2017

Last few bits were wrong for 128-byte write operation of SPI ip core in slave mode

When I was trying to implement SPI ip core and write 128-byte in slave mode back to master device, the last two or three bits were wrong as they were always 1. I have not tried to write more bytes to see if the issue is still there, but I think yes. So what the problem could it be? 

Additional to the issue above, we have another issue is that write data is not lined up with sck too well. If I set in mode 1 during write operation, master device can read it correctly. But it is not the perfect solution for this kind of issue, cause I must read data in mode 0 to get received data correctly.

Another thought is that the first issue would be cause by the second issue. So, the bits are shifted out as SPI controller recognized it as transaction has ended.

Any idea about those?

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