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Contributor
Contributor
1,146 Views
Registered: ‎06-07-2012

Memory allocation failure simulating Zynq-7000 VIP with Modelsim PE

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Hi,

 

I hit a very similar problem than Xil_user at https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Memory-allocation-failure-with-zynq-modelsim/m-p/512923#M34737 . I also read that should start a new thread (that thread is almost 4 years old...)  To summarize, I am trying to simulate a Zynq under Modelsim PE 10.6c.

 

Using Vivado 2017.4, I generate the base_zynq example design (which is a pretty empty design), exporting the design for Modelsim:

 

 export_simulation -simulator modelsim -of_objects [get_cells base_zynq_i] -lib_map_path c:/mti_libs/mtipe106/ -export_source_files -32bit

  

Then I start modelsim, create the modelsim_lib directory so the compilation can work, then: 

do compile.do

 

to compile everything. Then I start the simulation with: 

do simulation.do

 

 vip-fail.JPG

 Modelsim exits within 10 seconds on the failure. It looks funny that the allocated size above are exactly 0x8000 0010 and 0x8000 0000 (so exactly 2GB and 2GB+16Bytes.)

 

Has anybody ever simulated the Zynq VIP  with Modelsim PE?

 

Since Modelsim PE 10.5c and up is supported by Vivado 2017.4, I'd expect that I could use with the VIP.

 

Thank you,

 

jf

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Contributor
Contributor
1,310 Views
Registered: ‎06-07-2012

Re: Memory allocation failure simulating Zynq-7000 VIP with Modelsim PE

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Hi @demarco,

 

After reading your post, I upgraded my project from 2017.4 to 2018.1.

 

I also worked around the problem that I mentioned in my last post using multiple tops.  I could not trace the source of the problem, from my SystemVerilog top into the VHDL top, so instead I redid the architecture, putting the SystemVerilog as the top which only drives the VIP and then putting the VHDL simulation top instantiated under the SystemVerilog top.

 

So far so good.  This is slightly less elegant than multiple tops and we'll see if I have problem with the communication between the SV and VHDL, but so far it works, so we can 'close the case'.

 

Thanks,

 

jf

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Xilinx Employee
Xilinx Employee
1,101 Views
Registered: ‎10-04-2016

Re: Memory allocation failure simulating Zynq-7000 VIP with Modelsim PE

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Hi @jlarin,

The Xilinx Verification IPs (AXI VIP, Zynq VIP and MPSOC VIP) require simulators that support SystemVerilog and randomization. Please check with Mentor to see if these features are included in ModelSim.

 

In the past, ModelSim did not support these features and a Questa Prime license was required.

 

Regards,

 

Deanna

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Contributor
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Registered: ‎06-07-2012

Re: Memory allocation failure simulating Zynq-7000 VIP with Modelsim PE

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Hi @demarco,

 

I can confirm that Modelsim PE 10.6c does support SystemVerilog.  However looking for the randomization feature, I could only find the "SystemVerilog Constrained-Random Test Generation" in the Questa prime (and not Questa Core).  I can only guess that Modelsim PE won't support that feature.

 

Although it is strange that randomization would be required to do programmed AXI transaction (I just looked at the API and there are some random data transaction?),  I would recommend that those limitations be put the VIP datasheet.

 

Looking at DS940 (v1.0) April 28, 2017, in the simulation box, all I see is a link to the release notes which indicates that Modelsim PE is supported.

 

This being said, I switched to Vivado Simulator, which resolves the memory allocation failure.  However I see new problems.  I am trying to have a VHDL top level test bench since the whole project has been build in VHDL.  What I am working on now is a spinoff of a 3 year old project all build in VHDL.  It is unthinkable to redo all that validation infrastructure in Verilog just to include the Zynq VIP.

 

So my current test is to have multiple tops in the simulation.  I have the VHDL test bench set as top.  Much like the glbl.v is also included in the simulation through the elaboration phase, I added the systemVerilog testbench (copied from the example design) through the xsim.elaborate.xelab.more_options and it seems to work.

 

Much like the glbl.v, the system verilog is seen in the simulation scope.  I had to update the direct reference call:

        //tb.zynq_sys.base_zynq_i.processing_system7_0.inst.fpga_soft_reset(32'h1);

        vhdl_top_tb.dut.base_zynq_i.processing_system7_0.inst.fpga_soft_reset(32'h1);

 

That compile correctly.  The simulation runs.  But the simulation doesn't work. Should I open a new discussion to look into this, or do you have suggestion on how to achieve what I need (using the VIP with a VHDL testbench).

 

Thank you,

 

jf

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Xilinx Employee
Xilinx Employee
1,086 Views
Registered: ‎10-04-2016

Re: Memory allocation failure simulating Zynq-7000 VIP with Modelsim PE

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Hi @jlarin,

The Zynq VIP is built out of the AXI VIP IP (PG267). As you pointed out, some of the requirements to use AXI VIP that are in that notes that should be reflected in DS940 are not there. 

 

AXI VIP has timing randomization features built into it that cannot be disabled. Not all simulators support it.

 

Which version of the Vivado tools are you running? There were a number of fixes to the Zynq-7000 VIP that were released in 2018.1. 

 

Regards,

 

Deanna

 

 

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Contributor
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Registered: ‎06-07-2012

Re: Memory allocation failure simulating Zynq-7000 VIP with Modelsim PE

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Hi @demarco,

 

After reading your post, I upgraded my project from 2017.4 to 2018.1.

 

I also worked around the problem that I mentioned in my last post using multiple tops.  I could not trace the source of the problem, from my SystemVerilog top into the VHDL top, so instead I redid the architecture, putting the SystemVerilog as the top which only drives the VIP and then putting the VHDL simulation top instantiated under the SystemVerilog top.

 

So far so good.  This is slightly less elegant than multiple tops and we'll see if I have problem with the communication between the SV and VHDL, but so far it works, so we can 'close the case'.

 

Thanks,

 

jf

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