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Observer kg1
Observer
316 Views
Registered: ‎04-03-2016

Microblaze 16GB Extended Addressing - User Mode - No Data Access

Hi,

I am using the ZCU104 Evaluation Board with a 16GB SODIMM DDR4 Module connected to the PL side and I want to access the 16GB of data via the Microblaze processor.

I am using extended addressing which is set to 64GB and assigned the DDR4 memory addresses from 0x4_0000_0000 to 0x7_FFFF_FFFF. I also have a system ILA connected to the M_AXI_DP interface between the Microblaze and the AXI_Interconnnect, and another system ILA connected to the M_AXI between the AXI_Interconnect and the DDR4 MIG IP.

The Instruction and Data caches are disabled in the design.

The Microblaze has the Memory Management Unit enabled and configured to 'USERMODE' as I do not want virtualization. I just need to access the data directly via the Microblaze.

In turn this sets the following parameters in xparameters.h:
XPAR_MICROBLAZE_0_USE_MMU                1
XPAR_MICROBLAZE_0_ADDR_SIZE              36
XPAR_MICROBLAZE_0_DATA_SIZE               32
XPAR_MICROBLAZE_0_AREA_OPTIMIZED   0

Which should indicate that PAE is enabled and that the MMU is in USERMODE, according to UG984.

I then run code similar to the example in UG984 (pg.142):

{
u64 Addr = 0x0000_0004_0000_0000LL;
u8 Byte;

sbea(Addr, 0xA5);
Byte = lbuea(Addr);
}

But I don't witness any transactions occuring on the System ILAs.

I also read (UG984) that the instructions LBUEA and SBEA are privileged and require C_MMU_PRIVILEGED_INSTR between 2 or 3. I edited xparameters.h to reflect these values but I still had no success. 

Can anybody indicate what the problem might be? Or maybe indicate the proper procedure to use extended addressing? I can't find much material on this subject so any help would be greatly appreciated.

 

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4 Replies
Scholar jg_bds
Scholar
242 Views
Registered: ‎02-01-2013

Re: Microblaze 16GB Extended Addressing - User Mode - No Data Access

 

It looks like we might be in similar predicaments... See:

https://forums.xilinx.com/t5/Embedded-Development-Tools/Can-t-properly-access-memory-using-a-64-bit-MicroBlaze/m-p/1014752#M50249

The above post deals with accessing BRAM using a MicroBlaze with a 36-bit address bus, but we are having trouble accessing our 4-GB DDR4 interfaces, as well. (Problems occur using both 32-bit and 64-bit MicroBlazes...)

The only way we can get memory accesses to work, is by "compressing" everything to fit into a 4-GB space and resorting to a 32-bit-wide address for the MB.

Are you able to access your 16-GB DDR through other means--e.g., JTAG AXI or an IP?

-Joe G.

 

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Observer kg1
Observer
201 Views
Registered: ‎04-03-2016

Re: Microblaze 16GB Extended Addressing - User Mode - No Data Access

Hi Joe,
Thanks for posting.
Since I submitted the post above I have updated to Vivado 2019.1 in hopes that the 64-bit Microblaze would resolve my issue. But I was not successful. Whats worse is that I met with some weird behaviour from the 64-bit Microblaze as I posted here:
https://forums.xilinx.com/t5/Embedded-Processor-System-Design/64-bit-Microblaze-u64-variable-assigned-wrong-values/td-p/1014693

On the other hand, I have been able to access the 16GB DDR memory through the AXI DMA. I also performed a loop-back test using the AXI Traffic Generator which confirms that the data written is the same as the data being read back. However when I try to access the same addresses through the 'Memory Monitor' in SDK I don't get the same data values. So I am a bit uncertain at this point.

I will try using the JTAG to AXI Master soon and I'll get back to you with my results. Have you had any progress from your end?
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Scholar jg_bds
Scholar
187 Views
Registered: ‎02-01-2013

Re: Microblaze 16GB Extended Addressing - User Mode - No Data Access

 

Thanks for the reply.

We've been finding it hard to get traction.

We were able to write to BRAM (but not DRAM) yesterday using one design, but I'm not 100% sure that design wasn't compressed to 32-bits. (SW needs some HW to keep working, so we've provided them with a compressed design that fits into a 4-GB/32-bit address space.) That success has not been reproduced today.

We streamlined our 2018.3 version of a design somewhat by simplifying the AXI Interconnect, to aid in debug:

2019-09-05_11-35-07.jpg

We then instrumented it with an ILA, and noticed this:

2019-09-05_11-37-12.jpg

Somehow, the top 4 bits of the AXI Write Address are being presented as "F", instead of "0". The actual XSCT command was mwr -size D 0x90000000 0xaaaabbbbccccddd'. That's preventing a properly decoded access to BRAM (address 0x9000_0000). Note the "dec0de1c" being returned from AXI Interconnect as Read Data--because it has no idea what to do with the (erroneous) address(es) being presented to it.

Somehow, the MicroBlaze and XSDB/XSCT are not operating as expected. We are hoping that the means and methods to get it all working are simply eluding us right now.

-Joe G.

 

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Moderator
Moderator
169 Views
Registered: ‎09-12-2007

Re: Microblaze 16GB Extended Addressing - User Mode - No Data Access

As far as I know, the SW tools in 2019.1 only handles up to 40 bit address, unless you enable position independent code.

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