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Observer maria@tbg
Observer
3,410 Views
Registered: ‎01-31-2017

PS PL communication: code review

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Dear all

 

I'm sorry to post the question kind of twice (https://forums.xilinx.com/t5/BRAM-FIFO/polled-simple-DMA-example-with-VHDL-interface/td-p/764830/page/2) but since we are completely puzzled maybe someone in the "Zynq" forum could help us out.

 

The main issue is that every day we switch on the Zedboard we get different results, although we use the same source files! 

 

The goal is to transfer 32bits I generated in my VHDL IP block to PS.

I've got one self written IP block with a counter starting from 12 (hex C) to 43 (hex 2B) == 32bits.

I'm writing these 32bits to the "AXI Stream Data FIFO" block which is connected to the AXI DMA block.

 

From my previous post and the ILA, I think the PL is doing what it should do.

For the PS, I use the .c file from an example project (https://www.xilinx.com/support/answers/57561.html) where I deleted some parts regarding writing to the PL. Also the example project is running without problems, so we don't really expect anything going wrong on this end either.

 

Although it is such a "simple" VHDL code and .c file, a code review would be very much appreciated.

Additionally I've attached the results we can't really replicated the other day. On the first day it was running correctly except of the last value. Yesterday we could partially receive correct data. Today (we the same source files!) wrong data appears from "Value(8)".

 

Your help is very much appreciated,

Maria

 

screenshot_1705.png
screenshot_1805.png
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Observer maria@tbg
Observer
5,385 Views
Registered: ‎01-31-2017

Re: PS PL communication: code review

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Solved it.

 

Data is converted: so it's four u8 numbers combined into one u32.

s_axis_tdata <= std_logic_vector(index_counter_u8+3) & std_logic_vector(index_counter_u8+2) & std_logic_vector(index_counter_u8+1) & std_logic_vector(index_counter_u8) ;

 

If I change that in my VHDL and read u8 in C, it works.

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Scholar ericv
Scholar
3,393 Views
Registered: ‎04-13-2015

Re: PS PL communication: code review

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As you are on the ZedBoard, it's an A9 and not an A53, so __aarch64__ is not defined.

- key cache maintenance operations are not performed in your code.

 

The A9 memory used for the DMA source must be flushed & invalidated before starting the DMA transfer.

The A9 memory used for the DMA destination must be Invalidated before using it by the A9..

If you prefer, you can also flush and invalidate the destination memory before starting the DMA transfer

 

I hope this is helpful.

 

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Scholar ericv
Scholar
3,390 Views
Registered: ‎04-13-2015

Re: PS PL communication: code review

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More precisely:

 

//Xil_DCacheFlushRange((UINTPTR)TxBufferPtr, MAX_PKT_LEN);
#ifdef __aarch64__
	Xil_DCacheFlushRange((UINTPTR)RxBufferPtr, MAX_PKT_LEN*8);
#endif

should be only (is commented out with //)

Xil_DCacheFlushRange((UINTPTR)TxBufferPtr, MAX_PKT_LEN);

And after the transfer

	#ifndef __aarch64__
		Xil_DCacheInvalidateRange((UINTPTR)RxBufferPtr, MAX_PKT_LEN*4);
	#endif

Is OK... you can remove the #ifndef

But don't exceed the buffer size when invalidating as it could make data outside the buffer "disappear"

 

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Observer maria@tbg
Observer
3,295 Views
Registered: ‎01-31-2017

Re: PS PL communication: code review

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Hi ericv

 

thanks for your answer but we still get rubbish data at PS. (see screenshot attached)

Did you by any chance look at my VHDL code as well?

 

We are really puzzled, any help is very much appreciated.

 

Thanks,

Maria

screenshot_2205.png
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Scholar ericv
Scholar
3,205 Views
Registered: ‎04-13-2015

Re: PS PL communication: code review

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maria@tbg, I can't be of any help for the VHDL, I'm not even at the kindergarten level on that.

 

As you are dealing with 2 unknowns, the DMA and the cache memory, you should consider using uncached memory.

A memory area to uncache could be the on-chip RAM.

 

Regards

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Observer maria@tbg
Observer
3,130 Views
Registered: ‎01-31-2017

Re: PS PL communication: code review

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thanks for your help anyway ericv

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Observer maria@tbg
Observer
5,386 Views
Registered: ‎01-31-2017

Re: PS PL communication: code review

Jump to solution

Solved it.

 

Data is converted: so it's four u8 numbers combined into one u32.

s_axis_tdata <= std_logic_vector(index_counter_u8+3) & std_logic_vector(index_counter_u8+2) & std_logic_vector(index_counter_u8+1) & std_logic_vector(index_counter_u8) ;

 

If I change that in my VHDL and read u8 in C, it works.

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