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Visitor budaidai
Visitor
539 Views
Registered: ‎11-22-2018

PYNQ xfopencv jupyter notebooks

i follow https://github.com/Xilinx/PYNQ-ComputerVision/blob/master/overlays/README.md to make the xfopencv library to realise the function of  filter2D and dilate,but make wrong files(tcl,so,bit).

when i import the xv2overlay.so file,the error is as below.

TIM截图20181206195944.png

i find the size of so file and tcl file is smaller than the official file.

TIM截图20181206200827.png

when i make it ,i get the feedback.

ubuntu@ubuntu:/opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build$ cmake .. -DCMAKE_TOOLCHAIN_FILE=/opt/Xilinx/pynq_cv/frameworks/cmakeModules/toolchain_sdx2017.4.cmake -DSDxPlatform=/opt/Xilinx/SDx/2017.4/platforms/bare_hdmi -DSDxClockID=1 -DSDxArch=arm32
-- IN TOOLCHAINFILE: SDx platform: /opt/Xilinx/SDx/2017.4/platforms/bare_hdmi 
-- non default platform, please also set SDx clock ID (default clock ID is 0) and SDx arch (default is 64 bit)
-- SDx platform: /opt/Xilinx/SDx/2017.4/platforms/bare_hdmi , clock ID: 1, aarch: arm32 bit
-- SDx sysroot: /opt/Xilinx/SDx/2017.4/platforms/bare_hdmi/sw/sysroot
-- OpenCV library status:
--     version: 3.1.0
--     libraries: opencv_videostab;opencv_videoio;opencv_video;opencv_superres;opencv_stitching;opencv_shape;opencv_photo;opencv_objdetect;opencv_ml;opencv_imgproc;opencv_imgcodecs;opencv_highgui;opencv_flann;opencv_features2d;opencv_core;opencv_calib3d
--     include path: /opt/Xilinx/SDx/2017.4/platforms/bare_hdmi/sw/sysroot/usr/include/opencv;/opt/Xilinx/SDx/2017.4/platforms/bare_hdmi/sw/sysroot/usr/include
-- VIVADO HLS base path: /opt/Xilinx/Vivado/2017.4/
-- VIVADO HLS FOUND SO ON
-- VivadoHLS status:
--     found: ON
--     include path: /opt/Xilinx/Vivado/2017.4/include;/opt/Xilinx/Vivado/2017.4/include/hls
-- xfOpenCV CV base path: /opt/Xilinx/SDx/2017.4/include/xfopencv/include/
-- xfOpenCV FOUND SO ON
-- xfOpenCV include dirs: /opt/Xilinx/SDx/2017.4/include/xfopencv/include
-- PROJECT_SOURCE_DIR: /opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific
-- CMAKE_INCLUDE_PATH: /opt/Xilinx/SDx/2017.4/platforms/bare_hdmi/sw/sysroot/usr/
-- CMAKE_LIBRARY_PATH: /opt/Xilinx/SDx/2017.4/platforms/bare_hdmi/sw/sysroot/lib
-- CMAKE_PREFIX_PATH: 
-- Python    include path: /opt/Xilinx/SDx/2017.4/platforms/bare_hdmi/sw/sysroot/usr/include/python3.6m
-- Numpy     include path: /opt/Xilinx/SDx/2017.4/platforms/bare_hdmi/sw/sysroot/usr/lib/python3.6/site-packages/numpy/core/include
-- ADDING xv2overlay target
-- Creating xfFilter2D.cpp
-- Creating xfDilate.cpp
-- wrapper cpp file list src/xfFilter2D;src/xfDilate
-- working on flags for component filter2D
-- generating flags for filter2D
-- working on flags for component dilate
-- generating flags for dilate
-- SDxCompileFlags -sds-hw "xf::dilate<1,0,1080,1920,1>" xfDilate.cpp -files /opt/Xilinx/SDx/2017.4/include/xfopencv/include/imgproc/xf_dilation.hpp -clkid 1 -sds-end -sds-hw "xf::filter2D<1,3,3,0,0,1080,1920,1>" xfFilter2D.cpp -files /opt/Xilinx/SDx/2017.4/include/xfopencv/include/imgproc/xf_custom_convolution.hpp -clkid 1 -sds-end -fpic
-- INFO: libsds_lib.so found in /opt/Xilinx/SDx/2017.4/platforms/bare_hdmi/sw/sysroot/lib, adding as link library to target: xv2overlay
-- Configuring done
-- Generating done
-- Build files have been written to: /opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build
ubuntu@ubuntu:/opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build$ make xv2overlay -j2
[ 25%] Building CXX object CMakeFiles/xv2overlay.dir/src/xfFilter2D.o
[ 50%] Building CXX object CMakeFiles/xv2overlay.dir/src/xfDilate.o
Processing -sds-hw block for xf::filter2D<1,3,3,0,0,1080,1920,1>
Processing -sds-hw block for xf::dilate<1,0,1080,1920,1>
Platform system configuration option -sds-sys-config was not specified, searching for a configuration that uses the specified OS linux
Platform system configuration option -sds-sys-config was not specified, searching for a configuration that uses the specified OS linux
Using system configuration -sds-sys-config config0_0
Using system configuration -sds-sys-config config0_0
Create data motion intermediate representation
Create data motion intermediate representation
/opt/Xilinx/Vivado/2017.4/include/hls/hls_video_arithm.h:108:10: warning: '__ABS' macro redefined [-Wmacro-redefined]
#define __ABS(x) ( (x) >= 0 ? (x) : (-(x)))
 ^
/opt/Xilinx/SDx/2017.4/include/xfopencv/include/common/xf_params.h:40:9: note: previous definition is here
#define __ABS(X) ((X) < 0 ? (-(X)) : (X)) 
 ^
/opt/Xilinx/Vivado/2017.4/include/hls/hls_video_arithm.h:108:10: warning: '__ABS' macro redefined [-Wmacro-redefined]
#define __ABS(x) ( (x) >= 0 ? (x) : (-(x)))
 ^
/opt/Xilinx/SDx/2017.4/include/xfopencv/include/common/xf_params.h:40:9: note: previous definition is here
#define __ABS(X) ((X) < 0 ? (-(X)) : (X)) 
 ^
Performing accelerator source linting for w1_xf_dilate
Performing accelerator source linting for w0_xf_filter2D
Performing pragma generation
Performing pragma generation
INFO: [PragmaGen 83-3231] Successfully generated tcl script: /opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build/_sds/vhls/w1_xf_dilate.tcl
Moving function w1_xf_dilate to Programmable Logic
INFO: [PragmaGen 83-3231] Successfully generated tcl script: /opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build/_sds/vhls/w0_xf_filter2D.tcl
Moving function w0_xf_filter2D to Programmable Logic
sds++ log file saved as /opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build/_sds/reports/sds_xfFilter2D.log

[ 75%] Building CXX object CMakeFiles/xv2overlay.dir/src/cv_xilinx.o
Platform system configuration option -sds-sys-config was not specified, searching for a configuration that uses the specified OS linux
sds++ log file saved as /opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build/_sds/reports/sds_xfDilate.log

Using system configuration -sds-sys-config config0_0
Create data motion intermediate representation
/opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build/src/cv_xilinx.cpp:248:6: warning: function 'pyopencv_to<cv::KeyPoint>' has internal linkage but is not defined [-Wundefined-internal]
bool pyopencv_to(PyObject* obj, T& p, const char* name = "<unknown>");
 ^
/opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build/src/cv_xilinx.cpp:981:13: note: used here
 if(!pyopencv_to(item, value[i], info))
 ^
/opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build/src/cv_xilinx.cpp:251:11: warning: function 'pyopencv_from<cv::KeyPoint>' has internal linkage but is not defined [-Wundefined-internal]
PyObject* pyopencv_from(const T& src);
 ^
/opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build/src/cv_xilinx.cpp:994:26: note: used here
 PyObject* item = pyopencv_from(value[i]);
 ^
/opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build/src/cv_xilinx.cpp:248:6: warning: function 'pyopencv_to<cv::DMatch>' has internal linkage but is not defined [-Wundefined-internal]
bool pyopencv_to(PyObject* obj, T& p, const char* name = "<unknown>");
 ^
/opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build/src/cv_xilinx.cpp:981:13: note: used here
 if(!pyopencv_to(item, value[i], info))
 ^
/opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build/src/cv_xilinx.cpp:251:11: warning: function 'pyopencv_from<cv::DMatch>' has internal linkage but is not defined [-Wundefined-internal]
PyObject* pyopencv_from(const T& src);
 ^
/opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build/src/cv_xilinx.cpp:994:26: note: used here
 PyObject* item = pyopencv_from(value[i]);
 ^
Compiling /opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build/src/cv_xilinx.cpp
sds++ log file saved as /opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build/_sds/reports/sds_cv_xilinx.log

[100%] Linking CXX shared library libxv2overlay.so
Platform system configuration option -sds-sys-config was not specified, searching for a configuration that uses the specified OS linux
Using system configuration -sds-sys-config config0_0
Removing implementation files from previous run
Analyzing object files
... /opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build/CMakeFiles/xv2overlay.dir/src/xfFilter2D.o
... /opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build/CMakeFiles/xv2overlay.dir/src/xfDilate.o
... /opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build/CMakeFiles/xv2overlay.dir/src/cv_xilinx.o
... /opt/Xilinx/SDx/2017.4/platforms/bare_hdmi/sw/sysroot/usr/lib/libopencv_videostab.so.3.1.0
... /opt/Xilinx/SDx/2017.4/platforms/bare_hdmi/sw/sysroot/usr/lib/libopencv_superres.so.3.1.0
... /opt/Xilinx/SDx/2017.4/platforms/bare_hdmi/sw/sysroot/usr/lib/libopencv_stitching.so.3.1.0
... /opt/Xilinx/SDx/2017.4/platforms/bare_hdmi/sw/sysroot/usr/lib/libopencv_shape.so.3.1.0
... /opt/Xilinx/SDx/2017.4/platforms/bare_hdmi/sw/sysroot/usr/lib/libopencv_photo.so.3.1.0
... /opt/Xilinx/SDx/2017.4/platforms/bare_hdmi/sw/sysroot/usr/lib/libopencv_objdetect.so.3.1.0
... /opt/Xilinx/SDx/2017.4/platforms/bare_hdmi/sw/sysroot/usr/lib/libopencv_calib3d.so.3.1.0
... /opt/Xilinx/SDx/2017.4/platforms/bare_hdmi/sw/sysroot/usr/lib/libopencv_features2d.so.3.1.0
... /opt/Xilinx/SDx/2017.4/platforms/bare_hdmi/sw/sysroot/usr/lib/libopencv_ml.so.3.1.0
... /opt/Xilinx/SDx/2017.4/platforms/bare_hdmi/sw/sysroot/usr/lib/libopencv_highgui.so.3.1.0
... /opt/Xilinx/SDx/2017.4/platforms/bare_hdmi/sw/sysroot/usr/lib/libopencv_videoio.so.3.1.0
... /opt/Xilinx/SDx/2017.4/platforms/bare_hdmi/sw/sysroot/usr/lib/libopencv_imgcodecs.so.3.1.0
... /opt/Xilinx/SDx/2017.4/platforms/bare_hdmi/sw/sysroot/usr/lib/libopencv_flann.so.3.1.0
... /opt/Xilinx/SDx/2017.4/platforms/bare_hdmi/sw/sysroot/usr/lib/libopencv_video.so.3.1.0
... /opt/Xilinx/SDx/2017.4/platforms/bare_hdmi/sw/sysroot/usr/lib/libopencv_imgproc.so.3.1.0
... /opt/Xilinx/SDx/2017.4/platforms/bare_hdmi/sw/sysroot/usr/lib/libopencv_core.so.3.1.0
Generating data motion network
INFO: [DMAnalysis 83-4494] Analyzing hardware accelerators...
INFO: [DMAnalysis 83-4495] None of specified hardware accelerators found.
Removing implementation files from previous run /opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build/_sds/p0/_vpl
Removing implementation files from previous run /opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build/_sds/p0/vpl
Creating block diagram (BD)
Creating top.bd.tcl
/opt/Xilinx/SDx/2017.4/bin/cf2xd: 4: [: Linux: unexpected operator
/opt/Xilinx/SDx/2017.4/bin/cf2xd: 4: [: Linux: unexpected operator
/opt/Xilinx/SDx/2017.4/bin/cf_xsd: 4: /opt/Xilinx/SDx/2017.4/bin/cf_xsd: [[: not found
/opt/Xilinx/SDx/2017.4/bin/cf_xsd: 4: /opt/Xilinx/SDx/2017.4/bin/cf_xsd: [[: not found
Rewrite caller functions
Prepare hardware access API functions
Create accelerator stub functions
ERROR: [StubGen 83-4001] Fail to open file: /opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build/_sds/.llvm/w0_xf_filter2D.cfrewrite
ERROR: [StubGen 83-4001] Fail to open file: /opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build/_sds/.llvm/w1_xf_dilate.cfrewrite
Compile hardware access API functions
Compile accelerator stub functions
Preliminary link application ELF
Enable generation of hardware programming files
Enable generation of boot files
Calling VPL for partition 0

****** vpl v2017.4 (64-bit)
 **** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

INFO: [VPL 60-895] Target platform: /opt/Xilinx/SDx/2017.4/platforms/bare_hdmi/bare_hdmi.xpfm
INFO: [VPL 60-423] Target device: bare_hdmi
INFO: [VPL 60-251] Hardware accelerator integration...
Creating Vivado project and starting FPGA synthesis.
[02:27:33] Synthesis is running.
[02:28:33] Synthesis is running.
[02:29:33] Synthesis is running.
[02:30:33] Synthesis is running.
[02:31:33] Synthesis is running.
[02:32:34] Synthesis is running.
[02:33:34] Synthesis is running.
[02:34:34] Synthesis is running.
[02:35:34] Synthesis is running.
[02:36:34] Synthesis is running.
[02:37:34] Synthesis is running.
[02:38:34] Synthesis is running.
[02:39:34] Synthesis is running.
[02:40:34] Synthesis is running.
[02:41:34] Synthesis is running.
[02:42:34] Synthesis is running.
[02:43:34] Synthesis is running.
[02:44:34] Synthesis is running.
[02:45:34] Synthesis is running.
[02:46:34] Synthesis is running.
[02:47:34] Synthesis is running.
[02:48:34] Synthesis is running.
[02:49:50] Finished 1st of 6 tasks (FPGA synthesis). Elapsed time: 00h 23m 59s 

[02:49:50] Starting to link synthesized kernels..
[02:49:55] Phase 1 Generating reports.
[02:49:55] Phase 2 Done generating reports.
[02:50:47] Finished 2nd of 6 tasks (FPGA linking synthesized kernels to platform). Elapsed time: 00h 00m 57s 

[02:50:47] Starting logic optimization..
[02:50:47] Phase 1 Retarget
[02:50:52] Phase 2 Constant propagation
[02:50:52] Phase 3 Sweep
[02:50:52] Phase 4 BUFG optimization
[02:50:52] Phase 5 Shift Register Optimization
[02:51:03] Finished 3rd of 6 tasks (FPGA logic optimization). Elapsed time: 00h 00m 15s 

[02:51:03] Starting logic placement..
[02:51:08] Phase 1 Placer Initialization
[02:51:08] Phase 1.1 Placer Initialization Netlist Sorting
[02:51:08] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
[02:51:13] Phase 1.3 Build Placer Netlist Model
[02:51:13] Phase 1.4 Constrain Clocks/Macros
[02:51:13] Phase 2 Global Placement
[02:51:23] Phase 3 Detail Placement
[02:51:23] Phase 3.1 Commit Multi Column Macros
[02:51:23] Phase 3.2 Commit Most Macros & LUTRAMs
[02:51:23] Phase 3.3 Area Swap Optimization
[02:51:23] Phase 3.4 Pipeline Register Optimization
[02:51:23] Phase 3.5 Timing Path Optimizer
[02:51:23] Phase 3.6 Fast Optimization
[02:51:23] Phase 3.7 Small Shape Detail Placement
[02:51:29] Phase 3.8 Re-assign LUT pins
[02:51:29] Phase 3.9 Pipeline Register Optimization
[02:51:29] Phase 3.10 Fast Optimization
[02:51:29] Phase 4 Post Placement Optimization and Clean-Up
[02:51:29] Phase 4.1 Post Commit Optimization
[02:51:34] Phase 4.1.1 Post Placement Optimization
[02:51:34] Phase 4.1.1.1 BUFG Insertion
[02:51:34] Phase 4.2 Post Placement Cleanup
[02:51:34] Phase 4.3 Placer Reporting
[02:51:34] Phase 4.4 Final Placement Cleanup
[02:51:34] Finished 4th of 6 tasks (FPGA logic placement). Elapsed time: 00h 00m 31s 

[02:51:34] Starting logic routing..
[02:51:39] Phase 1 Build RT Design
[02:51:49] Phase 2 Router Initialization
[02:51:49] Phase 2.1 Create Timer
[02:51:49] Phase 2.2 Fix Topology Constraints
[02:51:49] Phase 2.3 Pre Route Cleanup
[02:51:54] Phase 2.4 Update Timing
[02:51:54] Phase 2.5 Update Timing for Bus Skew
[02:51:54] Phase 2.5.1 Update Timing
[02:51:54] Phase 3 Initial Routing
[02:52:00] Phase 4 Rip-up And Reroute
[02:52:00] Phase 4.1 Global Iteration 0
[02:52:00] Phase 4.2 Global Iteration 1
[02:52:00] Phase 5 Delay and Skew Optimization
[02:52:00] Phase 5.1 Delay CleanUp
[02:52:00] Phase 5.1.1 Update Timing
[02:52:05] Phase 5.2 Clock Skew Optimization
[02:52:05] Phase 6 Post Hold Fix
[02:52:05] Phase 6.1 Hold Fix Iter
[02:52:05] Phase 6.1.1 Update Timing
[02:52:05] Phase 7 Route finalize
[02:52:05] Phase 8 Verifying routed nets
[02:52:05] Phase 9 Depositing Routes
[02:52:05] Phase 10 Post Router Timing
[02:52:05] Finished 5th of 6 tasks (FPGA routing). Elapsed time: 00h 00m 31s 

[02:52:05] Starting bitstream generation..
[02:52:47] Creating bitmap...
[02:52:52] Writing bitstream ./top.bit...
[02:52:52] Finished 6th of 6 tasks (FPGA bitstream generation). Elapsed time: 00h 00m 47s 

INFO: [VPL 60-841] Created output file: /opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build/_sds/p0/vpl/system.bit
INFO: [VPL 60-841] Created output file: /opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build/_sds/p0/vpl/address_map.xml
INFO: [VPL 60-841] Created output file: /opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build/_sds/p0/vpl/system.hdf
INFO: [VPL 60-841] Created output file: /opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build/_sds/p0/vpl/_new_clk_freq
Software tracing enabled
Compile hardware access API functions
Link application ELF file
SD card folder created /opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build/sd_card
All user specified timing constraints are met.
sds++ log file saved as /opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build/_sds/reports/sds.log

[100%] Built target xv2overlay
ubuntu@ubuntu:/opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/build$ make install
[100%] Built target xv2overlay
Install the project...
-- Install configuration: ""
-- Installing: /opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/libarm32/xv2overlay.so
-- Installing: /opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/libarm32/xv2overlay.bit
-- Installing: /opt/Xilinx/pynq_cv/overlays/cvXfUserSpecific/libarm32/xv2overlay.tcl

 

 

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