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Observer posse
Observer
557 Views
Registered: ‎08-08-2018

Problem with SPI and CAN EMIO

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Hello,

I'm trying to set up a Zynq 7020 to communicate with another board through SPI and CAN, where the Zynq is the SPI slave. However, both the SPI and CAN signals are transmitted as LVDS on the cable.

I have been trying to convert each signal to LVDS within the PL. The way I'm going about this is routing the SPI and CAN interfaces to EMIO pins. Then individually route each interface signal to a SelectIO Interface wizard, configured to convert to LVDS25. Two SelectIO Wizards are used, one for input, and other for output.

This is the current block design:

Selection_001.png

The problem is that the synthesis returns the error "The connection to interface pin /processing_system7_0/CAN0_PHY_TX is being overridden by the user. This pin will not be connected as a part of interface connection CAN_0". Similar errors are returned for the other SPI and CAN signals.

Is there a way to convert the signals to LVDS, within the PL, or do I have to resort to external transceivers?

Thanks in advance

 

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Scholar jg_bds
Scholar
510 Views
Registered: ‎02-01-2013

Re: Problem with SPI and CAN EMIO

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I'm not sure if you really intend to munge those signals together like that--using those Interface Wizards--but if you only need to drive your low-speed signals out of the chip as differential LVDS signals, I'd take a different route:

2019-01-31_16-14-38.jpg

 

2019-01-31_16-28-45.jpg

-Joe G.

 

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4 Replies
Scholar jg_bds
Scholar
511 Views
Registered: ‎02-01-2013

Re: Problem with SPI and CAN EMIO

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I'm not sure if you really intend to munge those signals together like that--using those Interface Wizards--but if you only need to drive your low-speed signals out of the chip as differential LVDS signals, I'd take a different route:

2019-01-31_16-14-38.jpg

 

2019-01-31_16-28-45.jpg

-Joe G.

 

View solution in original post

Observer posse
Observer
485 Views
Registered: ‎08-08-2018

Re: Problem with SPI and CAN EMIO

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Thank you for the answer, the utility buffer really is the way to go, this block diagram helped a ton!

I just have one more question. As you may have realized, I'm trying to use the SPI interface as slave. However, the Zynq TRM states that when using SPI with EMIO pins, the SSx_SS_I pin should be tied high. However, in slave mode, I need that pin to input the SS signal. Furthermore, when performing design synthesis on Vivado, the same warning that the pin should be tied high comes up.

Will this be a problem, do I really need to tie the pin high, or the block diagram you presented will work just fine? I can't seem to find this information.

Thank you in advance

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Scholar jg_bds
Scholar
473 Views
Registered: ‎02-01-2013

Re: Problem with SPI and CAN EMIO

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Are you talking about this note regarding Master Mode SPI through EMIO/PL?

2019-02-01_8-44-48.jpg

You're not working in Master Mode.

See: https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Zynq-connect-PS-SPI-peripheral-through-EMIO-with-external-device/m-p/600394#M7321

-Joe G.

 

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Observer posse
Observer
465 Views
Registered: ‎08-08-2018

Re: Problem with SPI and CAN EMIO

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Yes, that was the note I was talking about. I failed however to understand that it was exclusively to master mode.

Thank you very much for the help, problem solved.

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