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Visitor thetrice
Visitor
2,432 Views
Registered: ‎03-30-2013

Problems with .ucf file for my microblaze system in ISE

ok so i added my microblaze from XPS generated a topvhdl file added the ucf file and in my microblaze i have 4 GPIO but i didnt put any of thier pins in the .ucf file although they are present as inout in the topvhdl but i was able to compile the project and gnerate a bitstream.
Now i commented out all the GPIO Pins in top vhdl and connected my microblaze system GPIO with internal signals as shown This also didnt case any trouble and i could generetate a bitstream.
Now what caused the problem is when i added the 7 ports of LED to external pins of my top vhdl file( which has nothing to do with my GPIO) it started telling me errors on the GPIO pins!!! here is the code :

-------------------------------------------------------------------------------
-- system_top.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity system_top is
  port (
    fpga_0_Ethernet_MAC_PHY_tx_clk_pin : in std_logic;
    fpga_0_Ethernet_MAC_PHY_rx_clk_pin : in std_logic;
    fpga_0_Ethernet_MAC_PHY_crs_pin : in std_logic;
    fpga_0_Ethernet_MAC_PHY_dv_pin : in std_logic;
    fpga_0_Ethernet_MAC_PHY_rx_data_pin : in std_logic_vector(3 downto 0);
    fpga_0_Ethernet_MAC_PHY_col_pin : in std_logic;
    fpga_0_Ethernet_MAC_PHY_rx_er_pin : in std_logic;
    fpga_0_Ethernet_MAC_PHY_rst_n_pin : out std_logic;
    fpga_0_Ethernet_MAC_PHY_tx_en_pin : out std_logic;
    fpga_0_Ethernet_MAC_PHY_tx_data_pin : out std_logic_vector(3 downto 0);
    fpga_0_Ethernet_MAC_PHY_MDC_pin : out std_logic;
    fpga_0_Ethernet_MAC_PHY_MDIO_pin : inout std_logic;
    fpga_0_DDR2_SDRAM_DDR2_Clk_pin : out std_logic;
    fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin : out std_logic;
    fpga_0_DDR2_SDRAM_DDR2_CE_pin : out std_logic;
    fpga_0_DDR2_SDRAM_DDR2_CS_n_pin : out std_logic;
    fpga_0_DDR2_SDRAM_DDR2_ODT_pin : out std_logic;
    fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin : out std_logic;
    fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin : out std_logic;
    fpga_0_DDR2_SDRAM_DDR2_WE_n_pin : out std_logic;
    fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin : out std_logic_vector(1 downto 0);
    fpga_0_DDR2_SDRAM_DDR2_Addr_pin : out std_logic_vector(12 downto 0);
    fpga_0_DDR2_SDRAM_DDR2_DQ_pin : inout std_logic_vector(15 downto 0);
    fpga_0_DDR2_SDRAM_DDR2_DM_pin : out std_logic_vector(1 downto 0);
    fpga_0_DDR2_SDRAM_DDR2_DQS_pin : inout std_logic_vector(1 downto 0);
    fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin : inout std_logic_vector(1 downto 0);
    fpga_0_DDR2_SDRAM_DDR2_DQS_Div_O_pin : out std_logic;
    fpga_0_DDR2_SDRAM_DDR2_DQS_Div_I_pin : in std_logic;
    fpga_0_clk_1_sys_clk_pin : in std_logic;
    fpga_0_rst_1_sys_rst_pin : in std_logic;
        LED : out std_logic_vector(0 to 7)--when i add this line it causses problems
--      xps_gpio_0_GPIO_IO_pin : inout std_logic_vector(0 to 31);--commented out the lines
--      xps_gpio_1_GPIO_IO_pin : inout std_logic_vector(0 to 31);
--      xps_gpio_2_GPIO_IO_pin : inout std_logic_vector(0 to 31);
--      xps_gpio_3_GPIO_IO_pin : inout std_logic_vector(0 to 31)
  );
end system_top;

architecture STRUCTURE of system_top is

  component system is
    port (
      fpga_0_Ethernet_MAC_PHY_tx_clk_pin : in std_logic;
      fpga_0_Ethernet_MAC_PHY_rx_clk_pin : in std_logic;
      fpga_0_Ethernet_MAC_PHY_crs_pin : in std_logic;
      fpga_0_Ethernet_MAC_PHY_dv_pin : in std_logic;
      fpga_0_Ethernet_MAC_PHY_rx_data_pin : in std_logic_vector(3 downto 0);
      fpga_0_Ethernet_MAC_PHY_col_pin : in std_logic;
      fpga_0_Ethernet_MAC_PHY_rx_er_pin : in std_logic;
      fpga_0_Ethernet_MAC_PHY_rst_n_pin : out std_logic;
      fpga_0_Ethernet_MAC_PHY_tx_en_pin : out std_logic;
      fpga_0_Ethernet_MAC_PHY_tx_data_pin : out std_logic_vector(3 downto 0);
      fpga_0_Ethernet_MAC_PHY_MDC_pin : out std_logic;
      fpga_0_Ethernet_MAC_PHY_MDIO_pin : inout std_logic;
      fpga_0_DDR2_SDRAM_DDR2_Clk_pin : out std_logic;
      fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin : out std_logic;
      fpga_0_DDR2_SDRAM_DDR2_CE_pin : out std_logic;
      fpga_0_DDR2_SDRAM_DDR2_CS_n_pin : out std_logic;
      fpga_0_DDR2_SDRAM_DDR2_ODT_pin : out std_logic;
      fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin : out std_logic;
      fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin : out std_logic;
      fpga_0_DDR2_SDRAM_DDR2_WE_n_pin : out std_logic;
      fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin : out std_logic_vector(1 downto 0);
      fpga_0_DDR2_SDRAM_DDR2_Addr_pin : out std_logic_vector(12 downto 0);
      fpga_0_DDR2_SDRAM_DDR2_DQ_pin : inout std_logic_vector(15 downto 0);
      fpga_0_DDR2_SDRAM_DDR2_DM_pin : out std_logic_vector(1 downto 0);
      fpga_0_DDR2_SDRAM_DDR2_DQS_pin : inout std_logic_vector(1 downto 0);
      fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin : inout std_logic_vector(1 downto 0);
      fpga_0_DDR2_SDRAM_DDR2_DQS_Div_O_pin : out std_logic;
      fpga_0_DDR2_SDRAM_DDR2_DQS_Div_I_pin : in std_logic;
      fpga_0_clk_1_sys_clk_pin : in std_logic;
      fpga_0_rst_1_sys_rst_pin : in std_logic;
        
      xps_gpio_0_GPIO_IO_pin : inout std_logic_vector(0 to 31);
      xps_gpio_1_GPIO_IO_pin : inout std_logic_vector(0 to 31);
      xps_gpio_2_GPIO_IO_pin : inout std_logic_vector(0 to 31);
      xps_gpio_3_GPIO_IO_pin : inout std_logic_vector(0 to 31)
    );
  end component;

  attribute BUFFER_TYPE : STRING;
 attribute BOX_TYPE : STRING;
  attribute BUFFER_TYPE of fpga_0_Ethernet_MAC_PHY_tx_clk_pin : signal is "IBUF";
  attribute BUFFER_TYPE of fpga_0_Ethernet_MAC_PHY_rx_clk_pin : signal is "IBUF";
 attribute BOX_TYPE of system : component is "user_black_box";
signal      xps_gpio_0_GPIO_IO :  std_logic_vector(0 to 31);
signal      xps_gpio_1_GPIO_IO :  std_logic_vector(0 to 31);
signal      xps_gpio_2_GPIO_IO :  std_logic_vector(0 to 31);
signal      xps_gpio_3_GPIO_IO :  std_logic_vector(0 to 31);
begin

  system_i : system
    port map (
      fpga_0_Ethernet_MAC_PHY_tx_clk_pin => fpga_0_Ethernet_MAC_PHY_tx_clk_pin,
      fpga_0_Ethernet_MAC_PHY_rx_clk_pin => fpga_0_Ethernet_MAC_PHY_rx_clk_pin,
      fpga_0_Ethernet_MAC_PHY_crs_pin => fpga_0_Ethernet_MAC_PHY_crs_pin,
      fpga_0_Ethernet_MAC_PHY_dv_pin => fpga_0_Ethernet_MAC_PHY_dv_pin,
      fpga_0_Ethernet_MAC_PHY_rx_data_pin => fpga_0_Ethernet_MAC_PHY_rx_data_pin,
      fpga_0_Ethernet_MAC_PHY_col_pin => fpga_0_Ethernet_MAC_PHY_col_pin,
      fpga_0_Ethernet_MAC_PHY_rx_er_pin => fpga_0_Ethernet_MAC_PHY_rx_er_pin,
      fpga_0_Ethernet_MAC_PHY_rst_n_pin => fpga_0_Ethernet_MAC_PHY_rst_n_pin,
      fpga_0_Ethernet_MAC_PHY_tx_en_pin => fpga_0_Ethernet_MAC_PHY_tx_en_pin,
      fpga_0_Ethernet_MAC_PHY_tx_data_pin => fpga_0_Ethernet_MAC_PHY_tx_data_pin,
      fpga_0_Ethernet_MAC_PHY_MDC_pin => fpga_0_Ethernet_MAC_PHY_MDC_pin,
      fpga_0_Ethernet_MAC_PHY_MDIO_pin => fpga_0_Ethernet_MAC_PHY_MDIO_pin,
      fpga_0_DDR2_SDRAM_DDR2_Clk_pin => fpga_0_DDR2_SDRAM_DDR2_Clk_pin,
      fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin => fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin,
      fpga_0_DDR2_SDRAM_DDR2_CE_pin => fpga_0_DDR2_SDRAM_DDR2_CE_pin,
      fpga_0_DDR2_SDRAM_DDR2_CS_n_pin => fpga_0_DDR2_SDRAM_DDR2_CS_n_pin,
      fpga_0_DDR2_SDRAM_DDR2_ODT_pin => fpga_0_DDR2_SDRAM_DDR2_ODT_pin,
      fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin => fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin,
      fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin => fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin,
      fpga_0_DDR2_SDRAM_DDR2_WE_n_pin => fpga_0_DDR2_SDRAM_DDR2_WE_n_pin,
      fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin => fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin,
      fpga_0_DDR2_SDRAM_DDR2_Addr_pin => fpga_0_DDR2_SDRAM_DDR2_Addr_pin,
      fpga_0_DDR2_SDRAM_DDR2_DQ_pin => fpga_0_DDR2_SDRAM_DDR2_DQ_pin,
      fpga_0_DDR2_SDRAM_DDR2_DM_pin => fpga_0_DDR2_SDRAM_DDR2_DM_pin,
      fpga_0_DDR2_SDRAM_DDR2_DQS_pin => fpga_0_DDR2_SDRAM_DDR2_DQS_pin,
      fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin => fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin,
      fpga_0_DDR2_SDRAM_DDR2_DQS_Div_O_pin => fpga_0_DDR2_SDRAM_DDR2_DQS_Div_O_pin,
      fpga_0_DDR2_SDRAM_DDR2_DQS_Div_I_pin => fpga_0_DDR2_SDRAM_DDR2_DQS_Div_I_pin,
      fpga_0_clk_1_sys_clk_pin => fpga_0_clk_1_sys_clk_pin,
      fpga_0_rst_1_sys_rst_pin => fpga_0_rst_1_sys_rst_pin,
      xps_gpio_0_GPIO_IO_pin => xps_gpio_0_GPIO_IO,--connected to a signal not any external pin
      xps_gpio_1_GPIO_IO_pin => xps_gpio_1_GPIO_IO,--connected to a signal not any external pin
      xps_gpio_2_GPIO_IO_pin => xps_gpio_2_GPIO_IO,--connected to a signal not any external pin
      xps_gpio_3_GPIO_IO_pin => xps_gpio_3_GPIO_IO--connected to a signal not any external pin
    );

end architecture STRUCTURE;

 Error message :

ERROR:Place:866 - Not enough valid sites to place the following IOBs:
   IO Standard: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR = BIDIR, DRIVE_STR = 12
   	xps_gpio_0_GPIO_IO_pin<0>
   	xps_gpio_0_GPIO_IO_pin<1>
   	xps_gpio_0_GPIO_IO_pin<2>
   	xps_gpio_0_GPIO_IO_pin<3>
   	xps_gpio_0_GPIO_IO_pin<4>
   	xps_gpio_0_GPIO_IO_pin<5>
   	xps_gpio_0_GPIO_IO_pin<6>
   	xps_gpio_0_GPIO_IO_pin<7>
   	xps_gpio_0_GPIO_IO_pin<8>
   	xps_gpio_0_GPIO_IO_pin<9>
   	xps_gpio_1_GPIO_IO_pin<0>
   	xps_gpio_1_GPIO_IO_pin<1>
   	xps_gpio_1_GPIO_IO_pin<2>
   	xps_gpio_1_GPIO_IO_pin<3>
   	xps_gpio_1_GPIO_IO_pin<4>
   	xps_gpio_1_GPIO_IO_pin<5>
   	xps_gpio_1_GPIO_IO_pin<6>
   	xps_gpio_1_GPIO_IO_pin<7>
   	xps_gpio_1_GPIO_IO_pin<8>
   	xps_gpio_1_GPIO_IO_pin<9>
   	xps_gpio_1_GPIO_IO_pin<10>
   	xps_gpio_1_GPIO_IO_pin<11>
   	xps_gpio_1_GPIO_IO_pin<12>
   	xps_gpio_1_GPIO_IO_pin<20>
   	xps_gpio_1_GPIO_IO_pin<13>
   	xps_gpio_1_GPIO_IO_pin<21>
   	xps_gpio_1_GPIO_IO_pin<14>
   	xps_gpio_1_GPIO_IO_pin<22>
   	xps_gpio_1_GPIO_IO_pin<30>
   	xps_gpio_1_GPIO_IO_pin<15>
   	xps_gpio_1_GPIO_IO_pin<23>
   	xps_gpio_1_GPIO_IO_pin<31>
   	xps_gpio_1_GPIO_IO_pin<16>
   	xps_gpio_1_GPIO_IO_pin<24>
   	xps_gpio_1_GPIO_IO_pin<17>
   	xps_gpio_1_GPIO_IO_pin<25>
   	xps_gpio_1_GPIO_IO_pin<18>
   	xps_gpio_1_GPIO_IO_pin<26>
   	xps_gpio_1_GPIO_IO_pin<19>
   	xps_gpio_1_GPIO_IO_pin<27>
   	xps_gpio_1_GPIO_IO_pin<28>
   	xps_gpio_1_GPIO_IO_pin<29>
   	xps_gpio_3_GPIO_IO_pin<10>
   	xps_gpio_3_GPIO_IO_pin<11>
   	xps_gpio_3_GPIO_IO_pin<12>
   	xps_gpio_3_GPIO_IO_pin<20>
   	xps_gpio_3_GPIO_IO_pin<13>
   	xps_gpio_3_GPIO_IO_pin<21>
   	xps_gpio_3_GPIO_IO_pin<14>
   	xps_gpio_3_GPIO_IO_pin<22>
   	xps_gpio_3_GPIO_IO_pin<30>
   	xps_gpio_3_GPIO_IO_pin<15>
   	xps_gpio_3_GPIO_IO_pin<23>
   	xps_gpio_3_GPIO_IO_pin<31>
   	xps_gpio_3_GPIO_IO_pin<16>
   	xps_gpio_3_GPIO_IO_pin<24>
   	xps_gpio_3_GPIO_IO_pin<17>
   	xps_gpio_3_GPIO_IO_pin<25>
   	xps_gpio_3_GPIO_IO_pin<18>
   	xps_gpio_3_GPIO_IO_pin<26>
   	xps_gpio_3_GPIO_IO_pin<19>
   	xps_gpio_3_GPIO_IO_pin<27>
   	xps_gpio_3_GPIO_IO_pin<28>
   	xps_gpio_3_GPIO_IO_pin<29>
   	xps_gpio_2_GPIO_IO_pin<0>
   	xps_gpio_2_GPIO_IO_pin<1>
   	xps_gpio_2_GPIO_IO_pin<2>
   	xps_gpio_2_GPIO_IO_pin<3>
   	xps_gpio_2_GPIO_IO_pin<4>
   	xps_gpio_2_GPIO_IO_pin<5>
   	xps_gpio_2_GPIO_IO_pin<6>
   	xps_gpio_2_GPIO_IO_pin<7>
   	xps_gpio_2_GPIO_IO_pin<8>
   	xps_gpio_2_GPIO_IO_pin<9>
   	xps_gpio_0_GPIO_IO_pin<10>
   	xps_gpio_0_GPIO_IO_pin<11>
   	xps_gpio_0_GPIO_IO_pin<12>
   	xps_gpio_0_GPIO_IO_pin<20>
   	xps_gpio_0_GPIO_IO_pin<13>
   	xps_gpio_0_GPIO_IO_pin<21>
   	xps_gpio_0_GPIO_IO_pin<14>
   	xps_gpio_0_GPIO_IO_pin<22>
   	xps_gpio_0_GPIO_IO_pin<30>
   	xps_gpio_0_GPIO_IO_pin<15>
   	xps_gpio_0_GPIO_IO_pin<23>
   	xps_gpio_0_GPIO_IO_pin<31>
   	xps_gpio_0_GPIO_IO_pin<16>
   	xps_gpio_0_GPIO_IO_pin<24>
   	xps_gpio_0_GPIO_IO_pin<17>
   	xps_gpio_0_GPIO_IO_pin<25>
   	xps_gpio_0_GPIO_IO_pin<18>
   	xps_gpio_0_GPIO_IO_pin<26>
   	xps_gpio_0_GPIO_IO_pin<19>
   	xps_gpio_0_GPIO_IO_pin<27>
   	xps_gpio_0_GPIO_IO_pin<28>
   	xps_gpio_0_GPIO_IO_pin<29>
   	xps_gpio_3_GPIO_IO_pin<0>
   	xps_gpio_3_GPIO_IO_pin<1>
   	xps_gpio_3_GPIO_IO_pin<2>
   	xps_gpio_3_GPIO_IO_pin<3>
   	xps_gpio_3_GPIO_IO_pin<4>
   	xps_gpio_3_GPIO_IO_pin<5>
   	xps_gpio_3_GPIO_IO_pin<6>
   	xps_gpio_3_GPIO_IO_pin<7>
   	xps_gpio_3_GPIO_IO_pin<8>
   	xps_gpio_3_GPIO_IO_pin<9>
   	xps_gpio_2_GPIO_IO_pin<10>
   	xps_gpio_2_GPIO_IO_pin<11>
   	xps_gpio_2_GPIO_IO_pin<12>
   	xps_gpio_2_GPIO_IO_pin<20>
   	xps_gpio_2_GPIO_IO_pin<13>
   	xps_gpio_2_GPIO_IO_pin<21>
   	xps_gpio_2_GPIO_IO_pin<14>
   	xps_gpio_2_GPIO_IO_pin<22>
   	xps_gpio_2_GPIO_IO_pin<30>
   	xps_gpio_2_GPIO_IO_pin<15>
   	xps_gpio_2_GPIO_IO_pin<23>
   	xps_gpio_2_GPIO_IO_pin<31>
   	xps_gpio_2_GPIO_IO_pin<16>
   	xps_gpio_2_GPIO_IO_pin<24>
   	xps_gpio_2_GPIO_IO_pin<17>
   	xps_gpio_2_GPIO_IO_pin<25>
   	xps_gpio_2_GPIO_IO_pin<18>
   	xps_gpio_2_GPIO_IO_pin<26>
   	xps_gpio_2_GPIO_IO_pin<19>
   	xps_gpio_2_GPIO_IO_pin<27>
   	xps_gpio_2_GPIO_IO_pin<28>
   	xps_gpio_2_GPIO_IO_pin<29>

 

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1 Reply
Xilinx Employee
Xilinx Employee
2,423 Views
Registered: ‎08-06-2007

Re: Problems with .ucf file for my microblaze system in ISE

Hi,

 

The GPIO pins are IN and OUT and thus only work as IO pin.

You have to remove them from the design since they are using IO resources.

 

Göran

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