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Registered: ‎02-10-2012

Question Regarding DDR_SDRAM's place in the PPC405 Address Map.

I was going throught the Create your own IP chapter in the Xilinx EDK Concepts Tools and Techniques guid and I came across this statement for their project example design flow:


"Verify that the address range for the DDR2_SDRAM is 0x88000000 – 0x8fffffff.
If this address has changed, change it back to the original value. "


(UG683 EDK 11.4 - Page : 73 , point number 23 )


Now I use Virtex 4 and in most of my PPC designs the  DDR_SDRAM is assigned from 0x00000000 to 0x03FFFFFF by default and I didnt change it . Is there any design flaw if the DDR_SDRAM uses this part of the PPC 405 address map ? Or is the initial part of the address map reserved for somethig special ? i didnt care about this much before but after reading the above statement it got me thinking. 


What do you guys think ?


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