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Observer tim99
Observer
544 Views
Registered: ‎08-16-2018

Question on AXI Quad SPI as a Slave

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Hi 

I have implemented rhe AXI Quad SPI IP core as a Slave in my FPGA.  

In simulation I have been driving the CS input dynamically with the clock and data and have seen no issues, BUT

when I handed this design over to the harware team, they could not get the core to work.  They reported a repeated first byte.

I have since found out that they are not driving cs dynamically, but are pulling it active all the time (active low).

I simulated this myself, and I see the same issues.

Looking back over the datasheet, I see this statement made on Page 44 (version v3.2) under the heading

Specification Exceptions
Exceptions from the Motorola M68HC11-Rev. 4.0 Reference
Manual

All SS signals are required to be routed between SPI devices internally to the FPGA.
This is because toggling of the SS signal is utilized in slaves to minimize FPGA
resources.

Does this imply that the IP only works with a dynamic CS, or is this a BUG ?

 

 

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Voyager
Voyager
464 Views
Registered: ‎02-01-2013

Re: Question on AXI Quad SPI as a Slave

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The situation you seem to be encountering is an exception to the serial communication protocol described in the M68HC11 datasheet, which the AXI Quad SPI IP Product Guide references as documentation of the "standard SPI protocol". I wouldn't say that it's a bug, since it's documented.

You are free to infer that "the IP only works with a dynamic CS", or you can just read this passage--and be sure:

2019-02-13_15-40-49.jpg

-Joe G.

 

4 Replies
Voyager
Voyager
465 Views
Registered: ‎02-01-2013

Re: Question on AXI Quad SPI as a Slave

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The situation you seem to be encountering is an exception to the serial communication protocol described in the M68HC11 datasheet, which the AXI Quad SPI IP Product Guide references as documentation of the "standard SPI protocol". I wouldn't say that it's a bug, since it's documented.

You are free to infer that "the IP only works with a dynamic CS", or you can just read this passage--and be sure:

2019-02-13_15-40-49.jpg

-Joe G.

 

Observer tim99
Observer
440 Views
Registered: ‎08-16-2018

Re: Question on AXI Quad SPI as a Slave

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Thanks for the reply, we figured that out in the end as a 'feature', however I didn't spot this in the datasheet I was looking at, all I saw was this: -

AXI Quad SPI v3.2 (PG153 April 4, 2018)

Exceptions from the Motorola M68HC11-Rev. 4.0 Reference
Manual

Specification Exceptions 

• All SS signals are required to be routed between SPI devices internally to the FPGA.
This is because toggling of the SS signal is utilized in slaves to minimize FPGA
resources

The sentance you highlight does indeed 'spell it out'

Thanks
Tim

 

 

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Visitor kpr29806
Visitor
294 Views
Registered: ‎04-17-2018

Re: Question on AXI Quad SPI as a Slave

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Hi @tim99, I think I'm having the same issue that you had back in February, but can't seem to solve it on my end.

I'm actually using two AXI QUAD SPI v3.2 cores to talk to each other - one configured as Master with the Manual Slave Select bit in the the Control Register set to 0 (to enable automatic toggling of SS); and one configured as a slave. I'm still seeing the same issue with a repeated first byte coming out of the Slave.

You can see a better description of my problem on my forum post here.

Any advice would be appreciated.

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Observer tim99
Observer
281 Views
Registered: ‎08-16-2018

Re: Question on AXI Quad SPI as a Slave

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Hi

This seems so long ago now.

We eventually solved this by ensuring that the SS toggled.  But bu by the sound of it, you are already doing this?

Regards

Tim

 

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