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Observer bj@mhlabs.com
Observer
558 Views
Registered: ‎12-09-2013

Resetting PS from PL (redux)

I would like to examine the possibility to reset the PS from the PL without an external connection to one of the external PS reset pins.

 

After looking at the TRM and various posts on the forum, it does not seem like there is any direct way to do this.

 

I am wondering if one of the following indirect ways may be possible:

 

  1. Use an AXI master connected to one of the GP ports to initiate a software reset via the SLCR:
    • Write the SLCR unlock
    • Set the SRST bit
  2. Implement a JTAG master in the PL that connects to the DAP and initiates a Debug System Reset

It seems to me that option 1 is simpler to do if it is possible.

 

Can anyone confirm that this may be a reasonable way to initiate a system reset? I already have an AXI Master that I could connect up and use to generate the register writes; however, setting that up is a lot of port connections, and I don't want to spend the time if it is just not going to work in the end...

 

TIA,

 

B.J.

 
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Observer bj@mhlabs.com
Observer
496 Views
Registered: ‎12-09-2013

Re: Resetting PS from PL (redux)

Nobody? 

 

Can anyone at Xilinx comment on the accessibility of the SLCR block from the PL AXI Masters?

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