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Observer cmuhlbauer
Observer
549 Views
Registered: ‎02-14-2018

SPI Module in Zynq US+ Devices Register Reference, UG1087

In the description of Config (SPI) Register, field CS, I believe the following statement is incorrect:

 

"Peripheral chip select lines; valid only if [Manual_CS] = 1."

 

I think this field is valid when Manual_CS = 0 or 1, otherwise Auto CS mode doesn't know which CS to assert.

 

Also,  the CS field S/B defined differently when PERI_SEL=1, but this definition is not provided

 

 

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3 Replies
Xilinx Employee
Xilinx Employee
521 Views
Registered: ‎06-06-2018

Re: SPI Module in Zynq US+ Devices Register Reference, UG1087

Hi @cmuhlbauer,

 

Config(SPI)Register, statement about MANUAL_CS = 1 or 0 is correct.

MANUAL_CS = 1 then we have to manually select the chip select lines.

MANUAL_CS = 0 then SPI core will automatically select the chip select lines.

 

For your query regarding "CS field S/B defined differently when PERI_SEL=1, but this definition is not provided"

 

You have to set MANUAL_CS=1 to allow external 3 to 8 decoder as shown in snapshot below.UG1087.PNG

 

Thanks and Regards,

Deepak D N

 

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Deepak D N
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Observer cmuhlbauer
Observer
505 Views
Registered: ‎02-14-2018

Re: SPI Module in Zynq US+ Devices Register Reference, UG1087

I am concerned that by just doing the 3-8 decode of the Slave Select signals glitches may occur on the inactive slave select decodes.  Is this a problem I should be concerned about? 

 

I wonder if Config (SPI) Register bit 13 is used to solve this problem since it doesn't have any other apparent use.

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Scholar ericv
Scholar
488 Views
Registered: ‎04-13-2015

Re: SPI Module in Zynq US+ Devices Register Reference, UG1087

@cmuhlbauer

 

As specified, if the controller is not actively transferring data, there are no issues with CS glitches.

SPI operates on clock transitions and there are no clock transitions when inactive.

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