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Observer mahdifpga
Observer
385 Views
Registered: ‎01-09-2018

Share DDR memory between two ARM processors on ZYNQ

Hi,

I have an Arty-Z7-20 board and my goal is to share the DDR memory between two cores in a way that I can read a big chunk of data (something in oder of 15 - 30 MB) on CPU#0 and put that into DDR memory, and then let the CPU#1 know when I am done via a flag (which I know how to do using OCM). Following this, I want CPU#1 to access the data that CPU#0 put in DDR and write it to the SD card, while CPU#0 starts to read the 2nd chunk of data and continue this alternatively. To do this, it is clear that I need to modify the ldscript of two projects, so they share part of the memory, but it seems whenever part of memory is shared between two cores, the 2nd core never works properly (most of the times, the 2nd core does not even start up). I believe memory overlap causes this.

I tried doing this routine using mailbox IP as well with smaller amount of data, however it never worked the way I expected and there were missing data points, even though Mailbox was never filling up. I doubt that Mailbox would be able to handle the data rate, so I have decided to use DDR memory directly. Does anybody know if my idea is practical or not, and if yes, how to do it? I have already read the whole XAPP 1079 and several smilar posts, but none of them have answered my questions. I am also trying to avoid using the Linux projects and just run two parallel bare-metal applications. 

Thanks,

Mahdi

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1 Reply
Xilinx Employee
Xilinx Employee
326 Views
Registered: ‎02-01-2008

Re: Share DDR memory between two ARM processors on ZYNQ

Both apps should run out of ddr without issue. But you have to be carefull during cache controller accesses such as flushing. It is easiest to just allow cpu0 to do the cache management.

Also, the USE_AMP define should be set for the cpu1 BSP. This will prevent cpu1 from corrupting the cache controller.

The cpu0 and cpu1 apps from xapp1079 should still work but comment out the code that takes cpu1 out of reset. And use the unmodified BSP from your current SDK install.This way you will not be dealing with having to customize the appropriate BSP to handle capturing the cpu after reset is released.

Also, start with using SDK system debug or xsct to debug the apps for both cpus.

FYI: the last time I posted updates to xapp1079 they were placed here: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842504/XAPP1079+Latest+Information

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