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Observer vgl94
Observer
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Registered: ‎06-11-2018

Simple Host to Memory bridge

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Hi,

I'm trying to use an FPGA evaluation board to bridge the host (computer) to a memory device (SSD) for a starter basis to my project. See the block design below:

forum.jpegBut I am getting the following errors:

 

(12x) [DRC REQP-52] connects_GTGREFCLK_ACTIVE: GTXE2_CHANNEL cell Main3_i/Host/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i: Use of the GTGREFCLK is reserved for test purposes only. This has the lowest performance of the available clocking methods and can degrade transceiver performance. Note that GTGREFCLK use may be caused by driving a REFCLK with a BUFG.
(3x) [DRC REQP-56] connects_GTGREFCLK_ACTIVE: GTXE2_COMMON cell Main3_i/Host/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i/qpll_wrapper_i/gtx_common.gtxe2_common_i: Use of the GTGREFCLK is reserved for test purposes only. This has the lowest performance of the available clocking methods and can degrade transceiver performance. Note that GTGREFCLK use may be caused by driving a REFCLK with a BUFG.

The first one I "solved" with the constraint

set_property SEVERITY WARNING [get_drc_checks REQP-52]
For the time being, but I was unable to find what the error was for both of them. They seem to be related. I tried to comment out some of the constraints (which I copied from another working project) but it still did not work.

The issue seems to be with the PCIe Host interface, some configuration of sorts attempts to enable the GTGREFCLK and I don't know why, because I copied this very same configuration from the Xilinx PCIe example. I have taken a look at the following links: 1, 2, 3 and 4.
The current board that I am using is the KC705 with my PC running with CentOS 7.6.1810.

The project is uploaded in here.

What is the recommended way to bridge a PC to a memory device?

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Observer vgl94
Observer
222 Views
Registered: ‎06-11-2018

Re: Simple Host to Memory bridge

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I just realised that this isn't possible with the KC705 board. At least with the hard IP core. Plus this error is related to using the Clocking Wizard to supply a frequency to the PCIe IP.

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Observer vgl94
Observer
223 Views
Registered: ‎06-11-2018

Re: Simple Host to Memory bridge

Jump to solution

I just realised that this isn't possible with the KC705 board. At least with the hard IP core. Plus this error is related to using the Clocking Wizard to supply a frequency to the PCIe IP.

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