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Adventurer
Adventurer
621 Views
Registered: ‎06-10-2013

The frequency of pl_clk0 is not correct.

Hi, everyone.

   In my design, a xczu3eg-sfva-625-1L-i chip is used. And recently, we found that the frequency of the pl_clk0 is not correct. My configurations are shown in the following figures. 

1.png2.png

In my design, i connect the pl_clk0 clock to an output pin, then i measure it with the chipscope, the frequency measured is 1 MHz.

Then, i change the PL0 output frequency to 10MHz, the frequency measured is still 1 MHz.

 

Is there anyone who knows the reason ? If you know ,please tell me.

 

Thanks.

 

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1 Reply
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Scholar
Scholar
599 Views
Registered: ‎02-27-2008

Re: The frequency of pl_clk0 is not correct.

Did you regenerate the entire design?  Restart the device and check it has loaded the new design?

 

Note the new design will have a new BOOT.BIN, FSBL, a uimage.ub (if there is an OS), and so on.

 

http://www.wiki.xilinx.com/Zynq+UltraScale+MPSoC+Non+Secure+Boot

Austin Lesea
Principal Engineer
Xilinx San Jose