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Registered: ‎05-30-2018

Ultra96 MPSoC - AXI DMA with ACP issues

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Hello everyone,

I am trying to set up a custom AXIS ip core, which gets and writes its data from/to the PS over the AXI DMA IP core operating in direct register mode.
It works correclty if I am using the HP port, but if I use the ACP port I get: DMASlvErr.
I did the following:

  • Fixed AxCACHE to 0xf
  • Fixed AxPROT to 0x2 (I am running it on a PetaLinux system)
  • Fixed AxUSER to be 0x0
  • Ensured that the address is 16/64byte aligned.

These are all the hints from this forum post. And I also looked through the coherency wiki but no new information was given. The only thing I can think of is that the AXI burst settings are wrong/illegal.
Looking at the TRM I read that the AxLEN has to be either 1 or 4 (after adding the implicit 1) and this is where I get confused. I have a 128-bit ACP data bus and I changed the datawidth in the DMA to 128 bit and set the max burst size to 16B, which means that the AxLEN should be set to zero, as one beat holds the data for the full burst and I assume that this is how the DMA interface derives the AxLEN but I am not sure.

Now of course I would verify it on my own with ILA but for some reason the two ultra96v1 boards crash if we open the Vivado Hardware Manger (2018.2/.3) with the single USB cable connected to the JTAG/UART pod from AVNET.

Is there any documentation on how the AXI DMA sets the AxLEN signals? Or how specifc values can be forced?

Looking through the forum a couple of posts (1, 2) said that the datamovers of the SDSoC versions don't support the ACP port, but this doesn't mean that it isn't supported for Vivado either, correct?

I added the block design and my settings of the AXI DMA in case I made a simple mistake.

Capture.PNGCapture1.PNG

All help is greatly appreciated,

Thanks

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-04-2016

Re: Ultra96 MPSoC - AXI DMA with ACP issues

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Hi @simple_student,

The max burst size setting in AXI DMA is the number of beats per a transfer, not the number of bytes. If you configure it to 16, you are actually sending 16 transfers * 16 bytes/transfer  = 256 bytes. That's much larger than a cache line size.

Do you get better results if you set the max burst size to 4? That would comply with the requirements of the ACP port.

Regards,

Deanna

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-04-2016

Re: Ultra96 MPSoC - AXI DMA with ACP issues

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Hi @simple_student,

The max burst size setting in AXI DMA is the number of beats per a transfer, not the number of bytes. If you configure it to 16, you are actually sending 16 transfers * 16 bytes/transfer  = 256 bytes. That's much larger than a cache line size.

Do you get better results if you set the max burst size to 4? That would comply with the requirements of the ACP port.

Regards,

Deanna

 

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Registered: ‎05-30-2018

Re: Ultra96 MPSoC - AXI DMA with ACP issues

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Thank you very much Deanna!

This solved my issues. But I must say that "Max Burst Size" != the burst "AxSIZE" signal is quite confusing.
But I guess, I should've hovered my mouse longer over this setting because it does say beats per burst
(as in AxLEN)...

Thanks again :)

 

 

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