04-18-2019 02:47 AM
Howdy All !
Not really sure in what group to post this as this is related to Vivado 2018.3 and UART Light.
Anyway, I maintain a bunch of reference designs, that we update to the latest Vivado suite as it becomes available.
With Vivado 2018.3, the UART Light stopped working. We use Xilinx development boards, and it doesn't seem to
matter what FPGA I target (Virtex 7, Kintex 7, Artix 7) the result is the same, no more TTY output from the UART Light.
I have created a simple test with a Microblaze, AXI Bram, and UART Light. Using the Sample "Hello World" Application - No UART output with Vivado 2018.3. If I create the same design in Vivado 2017.3, the UART/TTY output is as expected.
Attached is a complete archive of the UART Test design, all Xilinx components.
Any help/pointers appreicated !
I use CentOS 7.
04-30-2019 10:34 PM
Hi @asics.ws ,
Have you verified if BSP setting is proper for UART port in design against stdin/stdout?
This might cause no prints of applicatione execution.
04-30-2019 10:44 PM
yes, I have.
I regenerated it from scratch 3 times. Everything looks like it is properly connected.
The design is attached to my original post.
04-30-2019 11:32 PM
Attached are two screen shots that show the relevant settings.
And again, the same design works just fine with Vivado 2017.4. All problems started with Vivado 2018.3.