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Adventurer
Adventurer
9,227 Views
Registered: ‎03-03-2010

Vivado Block diagram not recognising full DDR Memory size

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I have a 1Gb DDR3 SDRAM chip attached to the FPGA (Zynq 702 Eval Board). The DDR3 is configured correctly in the Zynq settings, and I know it's correct because I chose the 702 board in the project settings:

 

2014-05-27-084259_1920x1080_scrot.png

 

However, when I try to allocate 1Gb of address space to the HP2 interface, it doesn't allow for me to go over 512 MB:

 

2014-05-27-084046_1920x1080_scrot.png

 

Even when execting the TCL command, I still get an error:

 

create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces axi_cdma_0/Data] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM
ERROR: [BD 41-1075] Cannot create address segment for </processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM> in </axi_cdma_0/Data> at 0x00000000[ 1G ] because proposed address <0x00000000[ 1G ]> is not a subset of fixed address range <0x00000000[ 512M ]>

 

How do I correctly map the SDRAM so that I can access the full 1GB?

 

1 Solution

Accepted Solutions
Adventurer
Adventurer
12,862 Views
Registered: ‎03-03-2010

Re: Vivado Block diagram not recognising full DDR Memory size

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I figured out a way around this:

 

open Project.srcs/sources_1/bd/design_1/design_1.bd

 

At the very end is the address mapping:

 

<spirit:segment>
<spirit:name>SEG_processing_system7_0_HP2_DDR_LOWOCM</spirit:name>
<spirit:displayName>/processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM</spirit:displayName>
<spirit:addressOffset>0x00000000</spirit:addressOffset>
<spirit:range>512M</spirit:range>
</spirit:segment>

 

This is what is populated into the GUI when the block diagram is opened. Change it to 1G.

 

<spirit:segment>
<spirit:name>SEG_processing_system7_0_HP2_DDR_LOWOCM</spirit:name>
<spirit:displayName>/processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM</spirit:displayName>
<spirit:addressOffset>0x00000000</spirit:addressOffset>
<spirit:range>1G</spirit:range>
</spirit:segment>

 

The Vivado gives a critical error, but you can still build the design and bitstream and it still works. 

 

View solution in original post

9 Replies
Xilinx Employee
Xilinx Employee
9,206 Views
Registered: ‎07-01-2010

Re: Vivado Block diagram not recognising full DDR Memory size

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Hi ,

What version of Vivado are you currently using?

Can you please share the tcl script?


Regards,
Achutha
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Xilinx Employee
Xilinx Employee
9,200 Views
Registered: ‎07-11-2011

Re: Vivado Block diagram not recognising full DDR Memory size

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Hi,

 

Please check this link and see if it applies for your case too

http://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/Vivado-2013-3-IP-integrator-address-editor-offset-address-can/td-p/394531

 

 

Regards,

Vanitha

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Adventurer
Adventurer
9,199 Views
Registered: ‎03-03-2010

Re: Vivado Block diagram not recognising full DDR Memory size

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It's vivado 2014.1

 

I can't really share the whole tcl script. However, I can share the zynq instance and and the address mapping sections:

 

# Create instance: processing_system7_0, and set properties
  set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.4 processing_system7_0 ]
  set_property -dict [ list CONFIG.PCW_EN_CLK1_PORT {0} CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {75} CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {0} CONFIG.PCW_USE_DMA0 {0} CONFIG.PCW_USE_FABRIC_INTERRUPT {0} CONFIG.PCW_USE_HIGH_OCM {1} CONFIG.PCW_USE_M_AXI_GP0 {1} CONFIG.PCW_USE_S_AXI_GP0 {0} CONFIG.PCW_USE_S_AXI_HP1 {1} CONFIG.PCW_USE_S_AXI_HP2 {1}  ] $processing_system7_0
create_bd_addr_seg -range 0x40000 -offset 0xFFFC0000 [get_bd_addr_spaces axi_cdma_0/Data] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_HIGH_OCM] SEG_processing_system7_0_HP1_HIGH_OCM create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_s

 

paces axi_cdma_0/Data] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM

 Is there anything in particular you're interested in?

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Adventurer
Adventurer
9,196 Views
Registered: ‎03-03-2010

Re: Vivado Block diagram not recognising full DDR Memory size

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I've seen that one before, it is about having a base address that is non-zero for the memory. In my case I have a baseaddress that is zero, it's just that the range can't go up to 1G.

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Adventurer
Adventurer
9,178 Views
Registered: ‎03-03-2010

Re: Vivado Block diagram not recognising full DDR Memory size

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I've thrown together a basic project that recreates the issue.

 

################################################################
# This is a generated script based on design: design_1
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################

################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2014.1
set current_vivado_version [version -short]

if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
   puts ""
   puts "ERROR: This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."

   return 1
}

################################################################
# START
################################################################

# To test this script, run the following commands from Vivado Tcl console:
# source design_1_script.tcl

# If you do not already have a project created,
# you can create a project using the following command:
#    create_project project_1 myproj -part xc7z020clg484-1
#    set_property BOARD_PART xilinx.com:zc702:part0:1.0 [current_project]


# CHANGE DESIGN NAME HERE
set design_name design_test

# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
#    create_bd_design $design_name

# CHECKING IF PROJECT EXISTS
if { [get_projects -quiet] eq "" } {
   puts "ERROR: Please open or create a project!"
   return 1
}


# Creating design if needed
set errMsg ""
set nRet 0

set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]

if { ${design_name} ne "" && ${cur_design} eq ${design_name} } {

   # Checks if design is empty or not
   if { $list_cells ne "" } {
      set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
      set nRet 1
   } else {
      puts "INFO: Constructing design in IPI design <$design_name>..."
   }
} elseif { ${cur_design} ne "" && ${cur_design} ne ${design_name} } {

   if { $list_cells eq "" } {
      puts "INFO: You have an empty design <${cur_design}>. Will go ahead and create design..."
   } else {
      set errMsg "ERROR: Design <${cur_design}> is not empty! Please do not source this script on non-empty designs."
      set nRet 1
   }
} else {

   if { [get_files -quiet ${design_name}.bd] eq "" } {
      puts "INFO: Currently there is no design <$design_name> in project, so creating one..."

      create_bd_design $design_name

      puts "INFO: Making design <$design_name> as current_bd_design."
      current_bd_design $design_name

   } else {
      set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
      set nRet 3
   }

}

puts "INFO: Currently the variable <design_name> is equal to \"$design_name\"."

if { $nRet != 0 } {
   puts $errMsg
   return $nRet
}

##################################################################
# DESIGN PROCs
##################################################################



# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {

  if { $parentCell eq "" } {
     set parentCell [get_bd_cells /]
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     puts "ERROR: Unable to find parent cell <$parentCell>!"
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj


  # Create interface ports

  # Create ports

  # Create instance: axi_cdma_0, and set properties
  set axi_cdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_cdma:4.1 axi_cdma_0 ]
  set_property -dict [ list CONFIG.C_M_AXI_DATA_WIDTH {64}  ] $axi_cdma_0

  # Create instance: axi_protocol_converter_0, and set properties
  set axi_protocol_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_protocol_converter:2.1 axi_protocol_converter_0 ]

  # Create instance: processing_system7_0, and set properties
  set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.4 processing_system7_0 ]
  set_property -dict [ list CONFIG.PCW_USE_S_AXI_HP1 {1}  ] $processing_system7_0

  # Create interface connections
  connect_bd_intf_net -intf_net axi_cdma_0_M_AXI [get_bd_intf_pins axi_cdma_0/M_AXI] [get_bd_intf_pins axi_protocol_converter_0/S_AXI]
  connect_bd_intf_net -intf_net axi_protocol_converter_0_M_AXI [get_bd_intf_pins axi_protocol_converter_0/M_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP1]

  # Create port connections

  # Create address segments
  create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces axi_cdma_0/Data] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
  

  # Restore current instance
  current_bd_instance $oldCurInst

  save_bd_design
}
# End of create_root_design()


##################################################################
# MAIN FLOW
##################################################################

create_root_design ""

 

 

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Adventurer
Adventurer
12,863 Views
Registered: ‎03-03-2010

Re: Vivado Block diagram not recognising full DDR Memory size

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I figured out a way around this:

 

open Project.srcs/sources_1/bd/design_1/design_1.bd

 

At the very end is the address mapping:

 

<spirit:segment>
<spirit:name>SEG_processing_system7_0_HP2_DDR_LOWOCM</spirit:name>
<spirit:displayName>/processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM</spirit:displayName>
<spirit:addressOffset>0x00000000</spirit:addressOffset>
<spirit:range>512M</spirit:range>
</spirit:segment>

 

This is what is populated into the GUI when the block diagram is opened. Change it to 1G.

 

<spirit:segment>
<spirit:name>SEG_processing_system7_0_HP2_DDR_LOWOCM</spirit:name>
<spirit:displayName>/processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM</spirit:displayName>
<spirit:addressOffset>0x00000000</spirit:addressOffset>
<spirit:range>1G</spirit:range>
</spirit:segment>

 

The Vivado gives a critical error, but you can still build the design and bitstream and it still works. 

 

View solution in original post

7,614 Views
Registered: ‎06-02-2014

Re: Vivado Block diagram not recognising full DDR Memory size

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Great tip, thank you it works for me as well. I have had this annoying issue for several versions of Vivado, now using 2014.4 and it is still there... I am using the ZedBoard with its board presets, not sure if it is relevant, but would be good if this can get fixed in future versions.

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Adventurer
Adventurer
5,980 Views
Registered: ‎03-03-2010

Re: Vivado Block diagram not recognising full DDR Memory size

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This bug fix doesn't work in 2014.4. The build image does not contain the correct memory map. 

 

However, Xilinx seems to have fixed this issue in its entirety in 2015.1. It seems to be possible to select 1G in the GUI now using that version.

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Explorer
Explorer
4,779 Views
Registered: ‎11-28-2011

Re: Vivado Block diagram not recognising full DDR Memory size

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Just received this error message when I tried to map the ACP LOW_OCM.  Was able to mitigate it by replicating what I had for HIGH_OCM and changing the offset address.

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