UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Moderator
Moderator
308 Views
Registered: ‎07-31-2012

Welcome to Embedded Processor System Design board

This board is intended to discuss Xilinx processor system design for Zynq UltraScale+ MPSoC/RFSoC, Zynq-7000, MicroBlaze, and PicoBlaze. This includes both Processor Subsystem (PS) peripherals and Programable Logic (PL) IP Peripherals that are not covered by other Xilinx forum boards such as Interrupts, UART, PS-SPI, USB, SATA, DDR, PS GEM, AXI Ethernet, SHIM logic, I2C, UART, CAN, CAN-FD, SYSMONs, RTC and GPIO. Additionally, includes the Vivado Processor Configuration Wizard (PCW), Clocking and Reset for Zynq-7000 and Zynq UltraScale+ SoCs.

 

The topics like Petalinux, QEMU belongs to Embedded Linux board and AXI DMA belongs to AXI Infrastructure board.

 

Before posting query, please follow the below steps:

  1. Search in the forum previous discussed similar topics
  2. Refer to useful resources -> IP product guide , user guide, relevant Wiki page menitoned in Xilinx IP hardware and software collateral
  3. Search for relevant AR/Known issues, limitations online
  4. Post your questions

 

Before posting, please read Xilinx Community Forums Guidelines or to get started see our Community Forum Help.

 


-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------