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Contributor
Contributor
12,496 Views
Registered: ‎05-27-2009

What motivates this error message and how to fix it

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Upon trying to download I get the following message

 

ELF file    : /home/flash/opt/Xilinx/11.1/EDK/../EDK/sw/lib/ppc405/ppc_bootloop.elf
elfcheck passed.
elfcheck completed successfully


Running command...
data2mem -bm /home/flash/opt/Xil_Proj/LL_fifo_2/implementation/system.bmm -bt /home/flash/opt/Xil_Proj/LL_fifo_2/implementation/system.bit  -bd /home/flash/opt/Xilinx/11.1/EDK/../EDK/sw/lib/ppc405/ppc_bootloop.elf tag ppc405_0 -o b /home/flash/opt/Xil_Proj/LL_fifo_2/SDK/.metadata/download.bit


ERROR:Data2MEM:47 - Not all BitLanes in ADDRESS_SPACE 'ppc405_0.plb_bram_if_cntlr_1_bram_combined' have BMM location constraints.
    Some data for this ADDRESS_SPACE may be lost during BIT file
    replacement. Verify that the BMM file has location constraints
    for all BitLanes.

      Bitlane(s)
   ----------------
   plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_0 [63:48]
   plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_1 [47:32]
   plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_2 [31:16]
   plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_3 [15:0]


ERROR:Data2MEM:47 - Not all BitLanes in ADDRESS_SPACE 'ppc405_0.ppc405_0_docm_cntlr_bram_combined' have BMM location constraints.
    Some data for this ADDRESS_SPACE may be lost during BIT file
    replacement. Verify that the BMM file has location constraints
    for all BitLanes.

      Bitlane(s)
   ----------------
   ppc405_0_docm_cntlr_bram/ppc405_0_docm_cntlr_bram/ramb16_0 [31:24]
   ppc405_0_docm_cntlr_bram/ppc405_0_docm_cntlr_bram/ramb16_1 [23:16]
   ppc405_0_docm_cntlr_bram/ppc405_0_docm_cntlr_bram/ramb16_2 [15:8]
   ppc405_0_docm_cntlr_bram/ppc405_0_docm_cntlr_bram/ramb16_3 [7:0]


ERROR:Data2MEM:47 - Not all BitLanes in ADDRESS_SPACE 'ppc405_0.ppc405_0_iocm_cntlr_bram_combined' have BMM location constraints.
    Some data for this ADDRESS_SPACE may be lost during BIT file
    replacement. Verify that the BMM file has location constraints
    for all BitLanes.

      Bitlane(s)
   ----------------
   ppc405_0_iocm_cntlr_bram/ppc405_0_iocm_cntlr_bram/ramb16_0 [63:48]
   ppc405_0_iocm_cntlr_bram/ppc405_0_iocm_cntlr_bram/ramb16_1 [47:32]
   ppc405_0_iocm_cntlr_bram/ppc405_0_iocm_cntlr_bram/ramb16_2 [31:16]
   ppc405_0_iocm_cntlr_bram/ppc405_0_iocm_cntlr_bram/ramb16_3 [15:0]

Failed to program the FPGA.

 

My mhs is attached.

 

What causes the error and how is it repaired?

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1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
15,720 Views
Registered: ‎08-08-2007

Re: What motivates this error message and how to fix it

Jump to solution

Hello,

 

Let me try to briefly explain the flow and how data2mem fits in the picture.  When you build an embedded system, the block RAM (BRAM) that is used for the system gets built to look like processor memory.  The BMM file describes how this BRAM is put together so that data2mem can use it.  The BMM file is first passed into NGDBuild.  But, it is only the name of the file that remains in the netlist.  When bitgen (the last tool to work on the netlist) received that place and routed NCD file, it recongnizes that there is a BMM file inside the netlist.  Bitgen will then read in the BMM file from your prject directory and produce a <project>_bd.bmm file.  This new BMM file contains the location information of all the BRAMs that the embedded system needs.  Data2mem will take your software application (most likely in ELF format) together with the new BMM file (<project_bd.bmm) and modify the .bit file to place the contents of the ELF into the BRAMs.  Data2mem can do this because it now knows the locations of all the BRAMs.

 

I hope that my explanation is clear.  Now to answer your queston:

 

"What motivates this error?"

 

The error happened becasue it appears that you passed data2mem the BMM file that normally gets passed into NGDBuild.

 

"How to fix it?"

 

Pass your BMM file to NGDBuild.  Wtih EDK, this is done automatically.  If you like everything command line :) then the swithc is the -bm switch for NGDBuild.  As you are running through the rest of the implementation tools, make sure that you BMM file reamins in the same project directory.  When bitgen completes, you should find your new BMM file with location information.  This is the file that you want to use with data2mem.

 

12 Replies
Xilinx Employee
Xilinx Employee
15,721 Views
Registered: ‎08-08-2007

Re: What motivates this error message and how to fix it

Jump to solution

Hello,

 

Let me try to briefly explain the flow and how data2mem fits in the picture.  When you build an embedded system, the block RAM (BRAM) that is used for the system gets built to look like processor memory.  The BMM file describes how this BRAM is put together so that data2mem can use it.  The BMM file is first passed into NGDBuild.  But, it is only the name of the file that remains in the netlist.  When bitgen (the last tool to work on the netlist) received that place and routed NCD file, it recongnizes that there is a BMM file inside the netlist.  Bitgen will then read in the BMM file from your prject directory and produce a <project>_bd.bmm file.  This new BMM file contains the location information of all the BRAMs that the embedded system needs.  Data2mem will take your software application (most likely in ELF format) together with the new BMM file (<project_bd.bmm) and modify the .bit file to place the contents of the ELF into the BRAMs.  Data2mem can do this because it now knows the locations of all the BRAMs.

 

I hope that my explanation is clear.  Now to answer your queston:

 

"What motivates this error?"

 

The error happened becasue it appears that you passed data2mem the BMM file that normally gets passed into NGDBuild.

 

"How to fix it?"

 

Pass your BMM file to NGDBuild.  Wtih EDK, this is done automatically.  If you like everything command line :) then the swithc is the -bm switch for NGDBuild.  As you are running through the rest of the implementation tools, make sure that you BMM file reamins in the same project directory.  When bitgen completes, you should find your new BMM file with location information.  This is the file that you want to use with data2mem.

 

Visitor hedink
Visitor
11,068 Views
Registered: ‎06-09-2010

Re: What motivates this error message and how to fix it

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I get a similar looking error,  however I am not modifying the edkbmmfile or the command line,  I can build and run normally until I try to add more than about 64k of bram to a processor then this error appears.

 

I am using ISE 14.1

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Observer mohanavels
Observer
10,749 Views
Registered: ‎07-22-2011

What motivates this error message and how to fix it

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Hi,

 

i am facing the problem of what you has explained.  But i am now to the EDK project, so i couldn't understand the problem.. plz heip to solve this problem...

 

Note: Here with, i have attached the ISE and EDK project window document.

 


ERROR:Data2MEM:47 - Not all BitLanes in ADDRESS_SPACE
'microblaze_0.microblaze_0_bram_block_combined' have BMM location constraints.
    Some data for this ADDRESS_SPACE may be lost during BIT file
    replacement. Verify that the BMM file has location constraints
    for all BitLanes.

      Bitlane(s)
   ----------------
   U3/microblaze_0_bram_block/microblaze_0_bram_block/ramb36e1_1 [15:0]
   U3/microblaze_0_bram_block/microblaze_0_bram_block/ramb36e1_0 [31:16]

ERROR:EDK:1001 - Data2Mem generated errors during execution
make: *** [implementation/download.bit] Error 1
ERROR:EDK - 
   Error while running "make -f MB.make init_bram".
ERROR: running XPS to load ELF data to bitstream failed.
ERROR: Bitstream data load failed, XPS did not generate D:/Aurora/DAQ_3011_ADC28_AD7983/Aurora/MB/implementation/download.bit

Process "Generate Programming File" failed

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Visitor andrecp
Visitor
10,577 Views
Registered: ‎01-22-2013

Re: What motivates this error message and how to fix it

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sorry elzinga but i am having the same problem as the OP and i can't fix it.. Your information is very good but the problem persists
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Explorer
Explorer
10,063 Views
Registered: ‎02-17-2013

Re: What motivates this error message and how to fix it

Jump to solution

Hey 

I search steps in order to realise a bootloader for my spartan 6. I start unfortunately I lost in the informations in the internet. 

When I execute this command I have a leak of memory. 

/home/mayotte/Xilinx/14.4/ISE_DS/ISE/bin/lin64/data2mem -bm system.bmm -bt system.bit -bd boot_esssai.elf output.bit

 

I place an examle of error that I can see in the console this is the latest. Do you have an idea why I have a leak of memory. 

 

INTERNAL_ERROR:Data2MEM:45 - Memory allocation leak of 8 bytes at 0x019B15F8 for 'CharPtrArrayType' data.
Total memory in use at allocation was 7605 bytes.
Source file "StringUtils.c", line number 901.

Memory contents:

019B15F8: 00 00 00 00 00 00 00 00

 

I have spartan 6 and I want programme the flash with a file who contains the  .elf and the .bit. I think  that with the impact 14.4 I load the file output.bit in the cable SPI. Unfortunately the file output.bit did'nt generate. I want know if I must add code in the main.c I download a project in this website of xilinx and in the file testApp.c they add this lines of code. 

I don't understand Do you can help me ? 

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Visitor wzinet
Visitor
9,669 Views
Registered: ‎08-07-2013

Re: What motivates this error message and how to fix it

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Hi,

 

Can you explain how to add the -bm switch to ISE?

 

I'm in a similar situation to the original poster, where I have a microblaze core, that I'm trying to integrate into an existing project.

 

When I duplicate the project, and leave only the instantiation of the mb the same (remove everything else) it works fine, but when I have the original project with all associated code, I get the error above (I'm using the exact same core in both cases), and the bmm files are identical in both cases.

 

If I right click on the 'implement' design menu, and go through the build options, I don't see a -bm anywhere, but again, I don't see how to add -bm to any of the steps either - is there a guide on how to do that?

 

Many thanks,

 

Will

  --

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Observer therealpaulie
Observer
9,528 Views
Registered: ‎11-18-2009

Re: What motivates this error message and how to fix it

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Hi,

 

I have the same problem. I added the -bm ..... *.bmm but I get now the same error as "tibacou". Did anyone get further? If yes please share how.

 

For Will: you just have to add at: Other Ngdbuild Command Line Option: "-bm ....... .bmm". There is no check box for it.

 

Thanks,

Paul

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Observer therealpaulie
Observer
9,525 Views
Registered: ‎11-18-2009

Re: What motivates this error message and how to fix it

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Hi again,

 

I made it work. So... here it comes:

 

1. Generate bit without the "-bm .... *.bmm" at translate. Otherwise you will get the 45 Error.

2. Open FPGA Editor (Implement Design / Place & Route / View-Edit Routed Design (FPGA Editor)

3. Search for the full name of the RAMBxx Modules. Compare it with the one from system_bd.bmm. Usually the instance name is different.

4. Modify system_bm.bmm in order to have exactly the same name as the one from FPGA editor. In my case the instance was "uC" and in *.bmm it was "mcs_0".

 

5. Now run Translate once again with the "-bm ... system_bd.bmm"

6. After everything is ready you'll get a system_bd_bmm.bmm in the same folder with system_bd.bmm. Replace the original with the new generated one. (If you compare these two files the you will notice that the location of the RAM Blocks is also there). Select NO when SDK asks you if you want to recover the modified file.

 

7. Go back in SDK and run it. It should work.

 

Regards,

Paul

8,653 Views
Registered: ‎03-07-2014

Re: What motivates this error message and how to fix it

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therealpaulie,

 

Thanks for you solution, it worked for me very well.

 

In implementing your solution I realized that all the "hard work" correcting the error can be avoided when the microblaze IP is being created in ISE. At that stage the instance should rather be named "mcs_0". I would imagine that on multiple microblaze processor designs the naming will follow a convention, i.e. the next one would be named "mcs_1", and so on.

 

Regards,

 

Ocaya

 

South Africa.

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2,808 Views
Registered: ‎03-07-2014

Re: What motivates this error message and how to fix it

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Here is a screenshot of ISE showing where the correction can be made.

 

Regards,

 

Ocaya

solution.png
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Visitor bobh
Visitor
2,538 Views
Registered: ‎12-11-2014

Re: What motivates this error message and how to fix it

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I was implementing a new block ram and controller to add to my microblaze and ran into this error.

 

Here's what I found.

The error is saying that some bram parts have no address.  You can see that this is true by looking in the edkBmmFile_bd.bmm file.

 

Block rams listed in the edkBmmFile.bmm are processed and the result is found in the edkBmmFile_bd.bmm.  Each item must be PLACED.

 

When I looked in edkBmmFile_bd.bmm it looked like this 

( a few lines from the file for the microblaze brams)

          PmpMicro_i/microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_4 RAMB16 [15:12] [0:4095] INPUT = microblaze_0_bram_block_combined_4.mem PLACED = X1Y26;
            PmpMicro_i/microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_5 RAMB16 [11:8] [0:4095] INPUT = microblaze_0_bram_block_combined_5.mem PLACED = X1Y24;
  (and a few lines from the same file for my bram)

           PmpMicro_i/bram_block_0/bram_block_0/ramb16bwer_4 RAMB16 [15:12] [0:4095] INPUT = bram_block_0_combined_4.mem;
            PmpMicro_i/bram_block_0/bram_block_0/ramb16bwer_5 RAMB16 [11:8] [0:4095] INPUT = bram_block_0_combined_5.mem;
   

NOTE that the microblaze brams (for data and instructions) were PLACED, but mine WERE NOT.

So my bram has no place on the FPGA and this is why you get error 45 (not all bit slices in Address space)

 

WHY DID THIS HAPPEN

In the MAP report, I found that MAP had deleted my bram !

 

WHY DID THAT HAPPEN

I had connected the port B inputs to external signals had not connected the Din port B output of the bram to anything  so with no output for port B and despite outputs for port A, MAP decided that this item was unused and could be trimmed.

 

HOW TO SOLVE IT

leave the input connections to external hardware and then connect the bram port B Din to the bram controller

Problem Solved

 

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1,509 Views
Registered: ‎02-02-2017

Re: What motivates this error message and how to fix it

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I have generated the following ram and rom from CoreGen:

 

component brom_im
 port (
	clka : IN std_logic;
	addra: IN std_logic_VECTOR(15 DOWNTO 0);
	douta: OUT std_logic_VECTOR(31 DOWNTO 0));
end component;

component bram_dm
 port (
	clka: IN std_logic;
	dina: IN std_logic_VECTOR(31 downto 0);
       addra: IN std_logic_VECTOR(15 downto 0);
	wea: IN std_logic_VECTOR(3 downto 0);
	douta: OUT std_logic_VECTOR(31 downto 0));
end component;

for which i have to write a BMM file. After place and route, I found the following instances names using PlanAhead.

 

BRAM_instance(bram_dm)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[46].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[53].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[59].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[57].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[44].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[47].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[49].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[62].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[54].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[45].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[43].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[58].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[48].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[60].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[31].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[55].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[50].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[52].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[56].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[51].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[63].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[61].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)

and 

BROM_instance (brom_im):
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[50].ram.r/v5_init.ram/SP.CASCADED_PRIM36.TDP_B (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[49].ram.r/v5_init.ram/SP.CASCADED_PRIM36.TDP_B (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[48].ram.r/v5_init.ram/SP.CASCADED_PRIM36.TDP_T (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[31].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[48].ram.r/v5_init.ram/SP.CASCADED_PRIM36.TDP_B (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[52].ram.r/v5_init.ram/SP.CASCADED_PRIM36.TDP_T (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[43].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[47].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[51].ram.r/v5_init.ram/SP.CASCADED_PRIM36.TDP_T (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[49].ram.r/v5_init.ram/SP.CASCADED_PRIM36.TDP_T (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[45].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[52].ram.r/v5_init.ram/SP.CASCADED_PRIM36.TDP_B (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[51].ram.r/v5_init.ram/SP.CASCADED_PRIM36.TDP_B (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[46].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[50].ram.r/v5_init.ram/SP.CASCADED_PRIM36.TDP_T (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[44].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)

Based on these primitives how can I write a correct BMM file.

 

Kind Regards

 

Sajjad
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