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Participant jimaandd
Participant
12,598 Views
Registered: ‎12-13-2009

Why I cannot set S2MM stream data width to 64 in AXI DMA 7.1 ?

Hi,

 

I started with my project using AXI DMA. My setup is as below:

 

(1) Simple DMA

(2) Only S2MM is enabled (Write channel).

(3) Memory Map data width and stream data width are both 64.

(4) Max Burst Size is 256.

 

My previous project is working on Planahead 14.5. The AXI DMA version is 6.0.3 a. It works perfectly as I expected. Now I want to switch to Vivado 2013.4. The DMA version is becoming 7.1. And the problem is that the stream data width is becoming to automatically  which I cannot edit for my setup. It kept as 32 which I want to 64 instead.

 

Untitled.jpg

 

According to the datasheet for AXI DMA 7.1.

"Data width in bits of the AXI S2MM AXI4-Stream Data bus. This value must be equal or less than the Memory Map Data Width. Valid values are 8, 16, 32, 64, 128, 512 and 1,024."

 

Based on my understanding, I should do that. But I don't know whether right now I cannot do it anymore. The only way I can do is "Enable Micro DMA" . At this setup, the Max Burst Size I chose will be 64. And I tried this and have some unexpected result. Since I don't know what Micro DMA exactly doing, I don't know where has issue.

 

Here I just wonder whether any one has the same concern. Is there any workaround I try to keep my old setup? I don't know why suddenly IP doesn't support it which makes it really annoying.

 

Thanks,

 

 

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19 Replies
Xilinx Employee
Xilinx Employee
12,594 Views
Registered: ‎08-02-2011

Re: Why I cannot set S2MM stream data width to 64 in AXI DMA 7.1 ?

This parameter is now set automatically based on the data width of whatever is driving the s2mm side of the AXI DMA. So what you need to do is check the upstream IP and change the tdata width that it is driving out. Then the AXI DMA will update accordingly.

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Participant jimaandd
Participant
12,586 Views
Registered: ‎12-13-2009

Re: Why I cannot set S2MM stream data width to 64 in AXI DMA 7.1 ?


@bwiec wrote:

This parameter is now set automatically based on the data width of whatever is driving the s2mm side of the AXI DMA. So what you need to do is check the upstream IP and change the tdata width that it is driving out. Then the AXI DMA will update accordingly.


 

Hi, bwiec,

 

Thank you for your answer.

 

I tried to created an custom IP with Master Stream AXI interface (64 bit width) and connect this IP to the S_AXIS_S2MM of DMA IP. And I get the warning message as below:

 

CRITICAL WARNING: [BD 41-237] Bus Interface property TDATA_NUM_BYTES does not match between /axi_dma_encoder/S_AXIS_S2MM(4) and /vh_AXIStream_0/M_AXI(8)
INFO: [BD 41-237] Bus Interface property NUM_WRITE_OUTSTANDING does not match between /processing_system7_0/S_AXI_HP0(8) and /axi_mem_intercon/s00_couplers/auto_pc/M_AXI(2)
INFO: [BD 41-237] Bus Interface property READ_WRITE_MODE does not match between /processing_system7_0/S_AXI_HP0(READ_WRITE) and /axi_mem_intercon/s00_couplers/auto_pc/M_AXI(WRITE_ONLY)
WARNING: [BD 41-235] Width mismatch when connecting pin: '/axi_dma_encoder/s_axis_s2mm_tkeep'(4) to net 'vh_AXIStream_0_M_AXI_TKEEP'(8) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/axi_dma_encoder/s_axis_s2mm_tdata'(32) to net 'vh_AXIStream_0_M_AXI_TDATA'(64) - Only lower order bits will be connected.

 

It is obviously not working. The S_AXIS_S2MM still keep 32 bit instead of 64 bit which I want.

 

Do you have more advice on it? I appreciate it.

 

Thanks,

 

 

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Participant jimaandd
Participant
12,585 Views
Registered: ‎12-13-2009

Re: Why I cannot set S2MM stream data width to 64 in AXI DMA 7.1 ?

Hi, Bwiec,

 

There is message is also interesting which I forgot to attach in last message. Please see below:

 

WARNING: [BD 41-702] Propagation TCL tries to overwrite parameter (C_M_AXI_S2MM_DATA_WIDTH) on /axi_dma_encoder that is set by user. Command ignored

 

 

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Xilinx Employee
Xilinx Employee
12,581 Views
Registered: ‎08-02-2011

Re: Why I cannot set S2MM stream data width to 64 in AXI DMA 7.1 ?

Hmm, it seems that parameter propagation isn't working. How are you creating your custom IP?
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Participant jimaandd
Participant
12,577 Views
Registered: ‎12-13-2009

Re: Why I cannot set S2MM stream data width to 64 in AXI DMA 7.1 ?


@bwiec wrote:
Hmm, it seems that parameter propagation isn't working. How are you creating your custom IP?

Hi, bwiec,

 

I created custom AXI IP according to XAPP 1168. Is there any requirement for the parameter for successfully propagation?

 

For example, if I creat an Master AXI stream IP to connect the S_AXIS_S2MM, what kind of parameters I should set? Right now I only set " TDATA_NUM_BYTES   :   integer := 8". Do you think it will be problem?

 

Please advise. Thanks,

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Participant jimaandd
Participant
12,538 Views
Registered: ‎12-13-2009

Re: Why I cannot set S2MM stream data width to 64 in AXI DMA 7.1 ?

Hi, Bwiec,

 

Do you think whether there is any workaound I can try?

 

Thanks a lot. I appreciate it.

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Xilinx Employee
Xilinx Employee
12,534 Views
Registered: ‎08-02-2011

Re: Why I cannot set S2MM stream data width to 64 in AXI DMA 7.1 ?

Hello,

Would it be possible to post your IP (you can strip out everything but the AXIS interface if you want)? I'll give it a try and see if I can figure out what's happening.
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Participant jimaandd
Participant
12,528 Views
Registered: ‎12-13-2009

Re: Why I cannot set S2MM stream data width to 64 in AXI DMA 7.1 ?


@bwiec wrote:
Hello,

Would it be possible to post your IP (you can strip out everything but the AXIS interface if you want)? I'll give it a try and see if I can figure out what's happening.

Hi, Bwiec,

 

Thank you for the answer.

 

What I did last time is trying to create an custom stream interconnect IP with 64 bit data width. My idea is to connect the master side to the dma  s2mm side, and make the slave side to connect to external pin. And if it works,  I can connect my FPGA 64 bit master axi stream interface to the external pins.

 

Since that, the custom stream interconnect IP is really simple. Attached zip file has such IP. As you know, right now I still cannot make the dma s2mm side data widht to be 64 although I connect it to my custom IP master side which is 64 bit width.

 

If have any question, please let me know. Thanks again,

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Participant jimaandd
Participant
12,471 Views
Registered: ‎12-13-2009

Re: Why I cannot set S2MM stream data width to 64 in AXI DMA 7.1 ?


@bwiec wrote:
Hello,

Would it be possible to post your IP (you can strip out everything but the AXIS interface if you want)? I'll give it a try and see if I can figure out what's happening.

Hi, Bwiec,

 

I found an work around to make the data width to be 64. Basically I manually change the C_S_AXI_S2MM_DATA_WIDTH to be 64 instead of 32 in the generated DMA IP. It finally works.

 

Here I have one question. Does Xilinx think this is an bug or not? If yes, can you suggest to solve this bug in the next Vivado release? I would like to know.

 

Thanks,

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Explorer
Explorer
7,595 Views
Registered: ‎09-19-2010

Re: Why I cannot set S2MM stream data width to 64 in AXI DMA 7.1 ?

Hi,
I have the same problem.

The Auto thing is not really Auto!

When you connect a 64 Bits width signal to the input port of the AXI DMA (to the S_AXIS_S2MM) it does not change the width of its tdata port to 64.

 

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Visitor cavila22
Visitor
7,210 Views
Registered: ‎03-14-2014

Re: Why I cannot set S2MM stream data width to 64 in AXI DMA 7.1 ?


@jimaandd wrote:

@bwiec wrote:
Hello,

Would it be possible to post your IP (you can strip out everything but the AXIS interface if you want)? I'll give it a try and see if I can figure out what's happening.

Hi, Bwiec,

 

I found an work around to make the data width to be 64. Basically I manually change the C_S_AXI_S2MM_DATA_WIDTH to be 64 instead of 32 in the generated DMA IP. It finally works.

 

Here I have one question. Does Xilinx think this is an bug or not? If yes, can you suggest to solve this bug in the next Vivado release? I would like to know.

 

Thanks,


Hi jimaandd,

 

In which file did u modify this? I am trying to work around this problem but without success.

 

Thanks

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Xilinx Employee
Xilinx Employee
7,206 Views
Registered: ‎08-02-2011

Re: Why I cannot set S2MM stream data width to 64 in AXI DMA 7.1 ?

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Visitor cavila22
Visitor
7,191 Views
Registered: ‎03-14-2014

Re: Why I cannot set S2MM stream data width to 64 in AXI DMA 7.1 ?

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Explorer
Explorer
7,038 Views
Registered: ‎09-08-2014

Re: Why I cannot set S2MM stream data width to 64 in AXI DMA 7.1 ?

I looked a the tread you suggest, which basically suggests fiddling about with the design until the auto detect see the change. I have tried doing as it suggests ie closing the block design and re-validating it and it makes no difference.

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Xilinx Employee
Xilinx Employee
7,031 Views
Registered: ‎08-02-2011

Re: Why I cannot set S2MM stream data width to 64 in AXI DMA 7.1 ?

What is upstream of the DMA? Are you 100% sure it is the data width you are expecting?
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Explorer
Explorer
7,027 Views
Registered: ‎09-08-2014

Re: Why I cannot set S2MM stream data width to 64 in AXI DMA 7.1 ?

I am absolutely certain as it was based on another design that was set correctly. I modified the design downstream of the DMA and the parameter changed. The blocks upstram of the VDMA remained unchanged.

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Visitor lucileklang
Visitor
3,747 Views
Registered: ‎06-28-2017

Re: Why I cannot set S2MM stream data width to 64 in AXI DMA 7.1 ?

Hi,

I also have the same problem, but I get 2 errors of the same kind :

CRITICAL WARNING: [BD 41-237] Bus Interface property TDATA_NUM_BYTES does not match between /xadc_axis_fifo_adapter_0/S_AXIS(2) and /spdif_0/M_AXISTREAM(4)
CRITICAL WARNING: [BD 41-237] Bus Interface property TDATA_NUM_BYTES does not match between /axi_dma_0/S_AXIS_S2MM(4) and /xadc_axis_fifo_adapter_0/M_AXIS(2)

 

I'm trying to implement an audio S/PDIF audio input, here's my design. Did this error got an effective solution ? I tried closing and re-opening BD, deleting and re-building the links between the blocks, nothing works.

 

Design SPDIF 2.PNG

At first I had only the first error, and I got the second one when I tried to fix it, by enabling MicroDMA. Seeing I got another error I disabled it but the error stayed.

Could someone give a solution to this problem ?
Thank you

 

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Visitor lucileklang
Visitor
3,734 Views
Registered: ‎06-28-2017

Re: Why I cannot set S2MM stream data width to 64 in AXI DMA 7.1 ?

Well actually fiddling worked for the error between the DMA and the FIFO adapter...
But I still have this error between the FIFO adapter and the SPDIF block, anyone to help ?

Here's a picture of the parameters I can change in the FIFO adapter :
xadc_fifo_adapter.PNG
The reason I use the FIFO adapter (that I stole in XAPP1183 which has an XADC instead of my SPDIF input) is to drive the tlast parameter. If I don't put it, I get an error that says that tlast is not connected as it should be.

Thanks !

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Visitor lucileklang
Visitor
3,694 Views
Registered: ‎06-28-2017

Re: Why I cannot set S2MM stream data width to 64 in AXI DMA 7.1 ?

If anyone is interested, I found a solution, which is actually very easy. There's a block  called AXI4-Stream Data Width Converter in Vivado that can be used to adapt the data width between 2 blocks with Axi Stream interfaces. I'm also pretty sure the same for normal AXI interfaces exists.