We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Registered: ‎07-03-2018

Wrong canonical definition for XADC Interrupt Register Bit definitions in xadcps_hw.h?

I found some difference about XADC Interrupt Register Bit definitions between xadcps_hw.h and page 25 of pg019_axi_xadc.pdf. Possibly some bits definition wrong, including XADCPS_INTX_ALM3_MASK, XADCPS_INTX_ALM4_MASK, XADCPS_INTX_ALM5_MASK, XADCPS_INTX_ALM6_MASK. Please help confirm it. Thanks!

1. XADC Interrupt Register Bit definitions in xadcps_hw.h

/** @name XADC Interrupt Status/Mask Register Bit definitions
  * The definitions are same for the Interrupt Status Register and
  * Interrupt Mask Register. They are defined only once.
  * @{
#define XADCPS_INTX_ALL_MASK          0x000003FF /**< Alarm Signals Mask  */
#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200 /**< CMD FIFO less than threshold */
#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100 /**< Data FIFO greater than threshold */
#define XADCPS_INTX_OT_MASK       0x00000080 /**< Over temperature Alarm Status */
#define XADCPS_INTX_ALM_ALL_MASK   0x0000007F /**< Alarm Signals Mask  */
#define XADCPS_INTX_ALM6_MASK       0x00000040 /**< Alarm 6 Mask  */
#define XADCPS_INTX_ALM5_MASK       0x00000020 /**< Alarm 5 Mask  */
#define XADCPS_INTX_ALM4_MASK       0x00000010 /**< Alarm 4 Mask  */
#define XADCPS_INTX_ALM3_MASK       0x00000008 /**< Alarm 3 Mask  */
#define XADCPS_INTX_ALM2_MASK       0x00000004 /**< Alarm 2 Mask  */
#define XADCPS_INTX_ALM1_MASK       0x00000002 /**< Alarm 1 Mask  */
#define XADCPS_INTX_ALM0_MASK       0x00000001 /**< Alarm 0 Mask  */

2. IP Interrupt Status Register (IPISR)Bit definitions on pg019_axi_xadc.pdf