UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor mprocca
Visitor
4,761 Views
Registered: ‎03-11-2015

XC7Z020 problems with the M_AXI_GP0 interface

We have PL defined registers that interface with PS through M_AXI_GP0. Bare Metal code running on core 1 accesses these registers.

 

1) repeated PS writes to a PL defined Tx FIFO register requires a software delay between writes or the write is not picked up by the PL
2) PS reads of a PL defined Tx FIFO count register usually will not show updated value even though it is decreasing internal to the PL

 

While the problems have surfaced with the Tx FIFO related registers, it may exist with other registers that are not used as often.

 

Anyone else seen this problem?

0 Kudos
1 Reply
Highlighted
Observer chengtms
Observer
4,746 Views
Registered: ‎11-24-2012

Re: XC7Z020 problems with the M_AXI_GP0 interface

I guess that might be a software problem. Did you declare your read and write variables as "volatile"?

e.g.

volatile int TxData;

volatile int TxCount;

....

*((int *)TXFIFO_DATA_REG) = TxData;

....

TxCount = *((int *)TXFIFO_COUNT);

....

 

With the volatile keyword the compiler will not assume that the content of those variables will remain unchanged between successive accesses. Therefore it needs to actually access those locations everytime to obtain the true values. It's a matter of compiler optimization.

 

Hope that helps.

 

Stephen

 

 

0 Kudos