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Visitor lsisaxon
Visitor
466 Views
Registered: ‎03-06-2018

XCZU3EG LPDDR4 Delay constraints clarification (CK to DQS), (DQ/DM/DQS grouping)

Hi,

 

I am nearing the end of my layout and I would like to have confirmation of the following before tapeout:-

 

1) I am not able to find the constraints for CK to DQS for LPDDR4. Is the DQS independent of CK for LPDDR4 and hence not necessary or does the information contained on pages 51, 52 and table 2-5 of UG583 (v1.12.1) is valid also for LPDDR4 regarding the DQS delay constraints?

 

2) Do the delays for DQ/DM to DQS (A) and DQ/DM to DQS (B) requires the entire word delay to be within the constraints or can I just typically break them into byte groups as follow? ie DQA[0-7] / DM0 / DQS0 as a group and DQA[8-15] / DM1 / DQS1 as another group that can have a different delay, and DQB[0-7] / DM2 / DQS2 and DQB[8-15] / DM3 / DQS3 as groups respectively, each with their own delay?

 

Or is it necessary to group DQA[0-15] / DM0 / DM1 / DQS0 / DQS1 as an entire group with the delay constraint and DQB[0-15] / DM2 / DM3 / DQS2 / DQS3 as another group?

 

Let me put it in another way, does the 5ps constrain for DQ/DM (slowest to fastest) (A) and DQ/DM (slowest to fastest) (B) on table 2-46 have to be across the entire DQ[0-15] and DM0/1 (A) or DM2/3 (B) or does it needs to be just within each of the byte group DQA[0-7]/DM0, DQA[8-15] /DM1, DQB[0-7]/DM2, DQB[8-15]/DM3?

 

I currently have 27ps (~4mm) between DQS0 to DQS1 and also DQS2 to DQS3 groups.

 

Thank you.

 

Best regards,

Saxon

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1 Reply
Adventurer
Adventurer
221 Views
Registered: ‎05-07-2008

Re: XCZU3EG LPDDR4 Delay constraints clarification (CK to DQS), (DQ/DM/DQS grouping)

Did you ever find the answer to your questions? I'm in the same situation and have the same questions.

Really wish Xilinx would do a better job at documenting this.

Thanks

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