We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Visitor nik_dan
Registered: ‎01-17-2018

Xapp1320 not working on zcu102 board

I have followed given in xapp1320,

Vivado 2017.3 is being used, with zcu102 board. on windows-10

following are the snapshot for settings:




IO_config (1).jpg


After making the bit file and transferring it to SDK, first there was an error while making R5_FSBL, it asked to add I2C_0, which I added, as you can make out in attached configurations image. Also, GEM-3 was removed, as otherwise there was MIO clash.


After boot.bit file was generated as instructed in xapp1320,  It was then, transferred to SD card and put in ZCU102 (SW-8 =. 1110).... the following was displayed on terminal and done LED went RED.


Xilinx Zynq MP First Stage Boot Loader 
Release 2017.3   Feb  5 2018  -  16:20:17
Reset Mode      :       System Reset
Platform: Silicon (4.0), Cluster ID 0xC0000100
Running on R5-0 Processor, Device Name: XCZU9EG
Initializing TCM ECC
Address 0xFFFD64A0, Length FFE00020, ECC initialized 
Address 0xFFFD64A0, Length FFE20000, ECC initialized 
Board Configuration successful 
Processor Initialization Done 
================= In Stage 2 ============ 
SD1 with level shifter Boot Mode 
SD: rc= 0
File name is 1:/BOOT.BIN
Multiboot Reg : 0x0 
Image Header Table Offset 0x8C0 
*****Image Header Table Details******** 
Boot Gen Ver: 0x1020000 
No of Partitions: 0x4 
Partition Header Address: 0x440 
Partition Present Device: 0x0 
Initialization Success 
======= In Stage 3, Partition No:1 ======= 
UnEncrypted data Length: 0x65216F 
Data word offset: 0x65216F 
Total Data word length: 0x65216F 
Destination Load Address: 0xFFFFFFFF 
Execution Address: 0x0 
Data word offset: 0x5220 
Partition Attributes: 0x26 
Destination Device is PL, changing LoadAddress
Please let me know, which configuration went wrong?
Please note, if following info is also helpful: while following UG-1209 
1. The PS memory test does not pass during BIST.
2. With Isolation configuration, it wasn't possible to run "hello world" on R5_0, though it worked while following it for vivado 2017.2 i.e without isolation
Thank you.
0 Kudos
5 Replies
Scholar austin
Registered: ‎02-27-2008

Re: Xapp1320 not working on zcu102 board

Note:  Xapp1320 is written for 2017.1,


No other versions are supported.  Please note what versions apply to what documents.

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
Visitor nik_dan
Registered: ‎01-17-2018

Re: Xapp1320 not working on zcu102 board



Sorry for the delayed response.

how should I perform the same task on 2017.3 then?

Please, tell the changes to be made for the same.



0 Kudos
Registered: ‎12-20-2013

Re: Xapp1320 not working on zcu102 board

I would like to run through XAPP1320 but I also have Vivado 2017.3. Would you recommended loading on the old software to enable the XAPP to work?


I don't really want to go back but I would be happy to go forward to the latest Vivado, if you know of any similar isolation  tutorial/examples that work. 

0 Kudos
Xilinx Employee
Xilinx Employee
Registered: ‎11-28-2007

Re: Xapp1320 not working on zcu102 board

Hi Nik_dan,

for the fsbl bitstream loading issue try setting XFSBL_PL_PWRUP_WAIT_MICROSEC to 10 in xfsbl_bs.h.

Alternatively check if timers are enabled (TTC) and accessible from R5.


Xilinx Employee
Xilinx Employee
Registered: ‎07-23-2015

Re: Xapp1320 not working on zcu102 board

There were some significant issues with the application note especially for software versions prior to 2018.1.  I just released a major update that should  address your issues.  However, it targets Vivado 2018 (tested on 2018.1 - 2018.3).