03-14-2012 12:31 PM
I am using a SP605.
I am using ISE 13.4 with a microblaze design that has an axi_quad_spi core attached to it.
I am configuring the FPGA from the SPI flash
If I use normal SPI mode to perform reads and writes, the configuration continues to wrok.
If I perform a quad-mode write operation, the configuration fails in any subsequent attempts.
i am not writing to the configuration area of the SPI as far as I know. I am rather sure of this, but can never be too sure.
I have a webcase open but that has been completely worhtless after 3 weeks of giving me suggestions and failing to read the information I provided or look at my project.
Is anyone else using Xilisf in quad mode? I do not see s single forum post about xilisf and quad mode.
Is anyone having this problem or has overcome it?
As a separate but possibly related isue, my data seems to be offset by 4 or 8 bytes such that writing a ramp from 0 to 255 into a 256 byte page of the flash and reading it back releaves everything shifted down by 4 or 8 values - seemingly mis-aligned in memory or somehow in the buffer. I think this could be my improper use/ignoring of the dummy bytes. I am pretty sure this is a separate issue.
Please post if you ahev any insight.
Xilinx has been completely worthless on this even though they tote this as one of the preferred methods of programming, especially for embedded designs.
03-14-2012 03:20 PM
What is the webcase number?
I can hardly believe this is a webcase with three weeks going unresolved (we wouldn't be in business if that was our level of service).
Once I have the webcase number, I will follow up and see why this is a problem, and get back to you,
03-14-2012 04:42 PM
I have a partial resolution in that I can run the interrupt driven, quad mode example, but my conversions to useable code for myself appears identical and yet fails.
<CASE:910621> Impact Indirect Programming and Configuration using Quad SPI
03-15-2012 07:29 AM
I have contacted support, and they are looking into it.
I apologize for the difficulties. Regardless of your level (small, medium, or large customer), there should not be any excessive delays in the resolution of a webcase.
If you have any further comments, feel free to email me directly at email@example.com
03-15-2012 07:34 AM
My webcase has changed hands and seems like it will be resolved today.
Thank you for your time and effort - I appreciate it.
04-05-2012 02:38 PM
What has been the resolution of this issue?
I am doing a new design with Spartan-6 with Winbond quad-SPI configuration flash. I noticed that the Winbond requires an extraordinary amount of time on power-up (up to 10msec) before it allows writes. If the Spartan-6 writes to the Winbond Control reg to set the Quad-Enable bit before the 10msec, there could be an error. If the Spartan-6 only uses the Winbond in normal SPI mode, Winbond reads can be done 10usec after power-up. This could explain your issue.
Note that the Winbond Quad-Enable bit does not have to set every time as it remembers during power cycling. Can the Spartan-6 configuration bypass the Quad-Enable bit setting to avoid writes?
04-05-2012 03:08 PM
After a 4 week webcase I finally settled with doing things the original way I had them.
I perform standard mode writes and quad reads and everything works fine.
Xilinx apparently does not know it's own core, nor to they have sample code doing anything useful or usable as is.
I was pointed to example file after example file of things I had already looked at and were not what I was trying to do.
I was able to perform quad writes immediately after configuration without problems, but they were actually slower than standard mode writes so I switched back. I do not know what the issue is exactly, but I cannot waste anymore time on this at this time.
Maybe one day Xilinx will figure out how to use their core or provide good examples and then the world will know how to use it too.
For now, just suffer on.
Sorry, and thanks for your help.