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Participant hariprasadb
Participant
386 Views
Registered: ‎04-23-2018

ZCU102 : Accessing PL DDR4 from Realtime R5 processor

Hello,

I am using ZCU102 to validate my Encoding IP. Here, I have the logic in FPGA(PL fabric) to write data samples to PL-DDR4 (using AUDIO_WRITE AXI MM Interface). Then R5 processor must read the these samples and do the encoding. I have defined 128M space for both Audio_write as well as ddr4_0 for Zynq_us_ss. Please refer to attached snapshot.

When I initiate the write, then I see the DDR4 address is going from 0000_0000 in the DDR4 controller AXI interface. Similarly, I have written bare metal application to read the written samples from R5, then if I initiate the read, then I am seeing the first address it is reading will be 0x0800_0000 although I specify the pointer address as  0xA800_0000 (no offset is added to the ddr4 base address, refer to atached snapshot).


#define DDR_BASEADDR_Audio 0xA8000000

int sample_buffer[2048];
int *bufferptr = (int *) DDR_BASEADDR_Audio;

for(i=0; i<2048; i++) {

sample_buffer[i]=bufferptr[i];

xil_printf("sample_buffer=%x bufferptr=%x\n",i,sample_buffer[i]);

}

I assume that, when FPGA is accessing, then the system is assigning first 128M space to FPGA logic (0x0 to 0x07fff_ffff) and for R5 it is auto assigning ddr address from 0800_0000 onwards.

Even, I tried to change the address of FPGA write logic to 0x0800_0000. But DDR4 write is not successful, looks like getting error response in bresp bus.

What is the setting to be done in bock diagram to access the same location from both fpga logic & R5.

 

With Regards,

Hariprasad Bhat

Block_diagram_DDR4.PNG
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1 Reply
Voyager
Voyager
333 Views
Registered: ‎02-01-2013

Re: ZCU102 : Accessing PL DDR4 from Realtime R5 processor

 

Based on your description, it appears that the PSU is presenting a 28-bit, 256-MB-aligned address (0x0800_0000) to the PL--even though the address range being accessed is only 128 MB deep--and an interconnect of some sort is declining to direct it to the DDR because address bit 27 is 1. Is that correct?

There are a couple of ways around this.

One would be to simply re-assign the PSU address for the PL DDR to 0x04_0000_0000. You seem to be using M_AXI_HPM0_FPD, and that is a valid address that has address bit 27 set to 0, so it should avoid the problem you're currently encountering. Your code may have to change to use 40-bit addresses, though.

Another way to handle it (a better way, IMHO) would be to have the PSU access the PL DDR access via M_AXI_HPM1_FPD, instead of M_AXI_HPM0_FPD. All of the peripherals can remain accessible to the PSU via M_AXI_HPM0_FPD, but the M_AXI_HPM1_FPD interface should connect to the PL DDR by connecting directly to the second AXI interconnect to which the other AXI write-masters connect.

In other words, I believe your system looks something like this:

2019-01-18_23-12-59.jpg

Get rid of the orange connection, and add the green one.

-Joe G.

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