UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor badmanjoe
Visitor
6,930 Views
Registered: ‎05-10-2013

ZYNQ on zedboard interfacing DS26518

Jump to solution

Hi guys,

 

i have a zedboard with ZYNQ processor running Linux and i would like to interface it with the 8 port E1 framer from maxim.

Can anyone please give me some guidllines or overview as to how i can interface with the DS26518 ?

 

Many thanks

0 Kudos
1 Solution

Accepted Solutions
Scholar austin
Scholar
9,043 Views
Registered: ‎02-27-2008

Re: ZYNQ on zedboard interfacing DS26518

Jump to solution

b,

 

Have you tried posting this on the zedboard.org forums?

 

What do you wish to do with this 8 portET1 framer?  Do you wish to process the digital data (payload) on each of the interfaces?  If so, you will need to use the programmable logic (PL or fabric) of the Zynq part.  I suggest you look at using the AXI streaming interfaces to input/output the streams to and from BRAM blocks in the fabric.

 

For example, suppose you wish to implement an echo canceller, you would accept the data from the 30 voice channels on each E1, and perform the echo cancellation either on the processors, or on the fabric, or partition the problem onto both.  8 x 30 = 240 voice channels, so every 125 microseconds, you have to have 240 bytes ready to go back out on the E1's.

 

That is about two bytes processed every microsecond.  I doubt seriously you can do this with the ARM A9's, as that is 1280 CPU cycles at 667 MHz.  Sounds like a lot of cycles, but if you are running linux, which is not a real time operating system, it is unlikely you will be able to do this echo cancelling entirely in software, thus, you will need to do most of the job in hadrware (adaptive digital filter).  The hardware of the FPGA is very well suited to massive parallelism, as building 240 adapative filters is probably not all that difficult, and running them at 8 KHz means there is hardly any dynamic power at all (much, much lower power than using a DSP for example).

 

You might consider pprogramming this all in c, and using the Vivado HLS to move the c to the fabric.  The c code forms the testbench, so you always know if you are doing the right thing.

 

Good luck, and have fun!

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post

0 Kudos
11 Replies
Scholar austin
Scholar
9,044 Views
Registered: ‎02-27-2008

Re: ZYNQ on zedboard interfacing DS26518

Jump to solution

b,

 

Have you tried posting this on the zedboard.org forums?

 

What do you wish to do with this 8 portET1 framer?  Do you wish to process the digital data (payload) on each of the interfaces?  If so, you will need to use the programmable logic (PL or fabric) of the Zynq part.  I suggest you look at using the AXI streaming interfaces to input/output the streams to and from BRAM blocks in the fabric.

 

For example, suppose you wish to implement an echo canceller, you would accept the data from the 30 voice channels on each E1, and perform the echo cancellation either on the processors, or on the fabric, or partition the problem onto both.  8 x 30 = 240 voice channels, so every 125 microseconds, you have to have 240 bytes ready to go back out on the E1's.

 

That is about two bytes processed every microsecond.  I doubt seriously you can do this with the ARM A9's, as that is 1280 CPU cycles at 667 MHz.  Sounds like a lot of cycles, but if you are running linux, which is not a real time operating system, it is unlikely you will be able to do this echo cancelling entirely in software, thus, you will need to do most of the job in hadrware (adaptive digital filter).  The hardware of the FPGA is very well suited to massive parallelism, as building 240 adapative filters is probably not all that difficult, and running them at 8 KHz means there is hardly any dynamic power at all (much, much lower power than using a DSP for example).

 

You might consider pprogramming this all in c, and using the Vivado HLS to move the c to the fabric.  The c code forms the testbench, so you always know if you are doing the right thing.

 

Good luck, and have fun!

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post

0 Kudos
Visitor badmanjoe
Visitor
6,910 Views
Registered: ‎05-10-2013

Re: ZYNQ on zedboard interfacing DS26518

Jump to solution

Austin, thank you very much for your reply. it helps alot!

 

 

0 Kudos
Scholar austin
Scholar
6,899 Views
Registered: ‎02-27-2008

Re: ZYNQ on zedboard interfacing DS26518

Jump to solution

I am glad I could help,

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
Visitor badmanjoe
Visitor
6,885 Views
Registered: ‎05-10-2013

Re: ZYNQ on zedboard interfacing DS26518

Jump to solution

Hello Austin,

 

For a starter, what iwould like to do is accumulate up to 240 bytes (30 msec) from each channel and send it on LAN. (thats 32 channels x 8 E1 ports). The additional data compression to remove empty time slots.

To do so i have two approaches.

 

First im thinking to use the PS system alone. As the ZYNQ has 2 cores PS1 and PS2, im thinking to have PS1 (running C code) to access the E1 framer and store the data into a shared memory (ddr3??), while Ps2 (running RTOS for easy definition of IP stack) will fetch the data from memory and send it to LAN.

So basically i have each E1 port running at 2.048Mbps (8 ports), which means PS1 has to process 1 byte of data and store it into memory every 500ns. Do you think that would be doable?

 

My second approach is to use the PL/fabric. where i will create 8  'designs/modules' in parallel where each one reads one E1 port and process it. in this case the PL will function at 256Khz (8khz x 32 channel for each port). it will process the data, combine each 4 bytes into 1 word (32bit) and store it into a BRAM(32 bit wide) - i will use 64 RAM blocks (got 32*8 channels devided by 4).

Data will then be transfered from the BRAM in the fabric to the PS where it will be sent to LAN. This will be done by the AXI-streaming interface.

The third option would be writing the data from the PL to the DDR3, which is read by the PS and sent to LAN.

 

I will greatly appreciate it if you give me your opinion regarding this matter!

 

Regards

0 Kudos
Scholar austin
Scholar
6,880 Views
Registered: ‎02-27-2008

Re: ZYNQ on zedboard interfacing DS26518

Jump to solution

b,

 

The first option won't work, as if you use the DDR memory, there are fairly long wait times for addressing.  It might work if you used the BRAM as a buffer/fifo, and used the streaming AXI inreface.  I would collect wide wordsw (at least 32 bits), if not 64 bit wide, and operate entirely on the wider words (lower clock frequencies makes it easier for the tools to meet timing).  I would use the HP (high performance) port, from the PL over to the PS.  Dedicating one core to process the data is a good idea (so you don't lose data when the processor gets an interrupt).

 

One question, back to you:  how do you know a time slot is empty?  How is the data formatted?  If it is voice, then you could ignore channels that are "on-hook" (not talking).

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
Visitor badmanjoe
Visitor
6,854 Views
Registered: ‎05-10-2013

Re: ZYNQ on zedboard interfacing DS26518

Jump to solution

Hi Austin,

 

Sorry for the late reply! and thank you again for yours!

 

Yes, this is voice data that im recording. What do you mean "on-hook".

To know if a timeslot is empty i though to deframe the data, look at the bit pattern and decide from there. It depends on the system used ofcourse, but there are bit patterns for silence such as u-low,a-low.

 

So basically you dont think i could write to DDR from the PL and read from the DDR via PS at the same time? Hmm i was hoping that would work!

I will definately keep you updated with my progress :) this is basically my first challenge with the zedboard

0 Kudos
Visitor badmanjoe
Visitor
6,848 Views
Registered: ‎05-10-2013

Re: ZYNQ on zedboard interfacing DS26518

Jump to solution

Austin, another question for you :)

 

The Zynq has two processors and I realise now that probably one of the PS (1) must be used to access the E1 framer and deposit the data to a shared memory where the other PS (2) can fetch data andsend it to LAN.   PS1 will be implemented running C code with no OS (Bare Metal) and PS2 will use Linux or FreeRTOS to host the application for easy access to the IP stack and other facilities.

I want to also accumulate 240 bytes from each channel before sending to LAN. And each E1 ports run at 2.048Mbps.. so if i wanted to use the PS only, i need it running at 2.048*8 = 16.384 Mhz atleast.. which is possible as the cores on the zynq run at 667Mhz.

Why cant I use the internal 256Kbye memory of the zynq to store the received data and then send it to LAN. How fast does the internal SRAM run at? If not, then how fast can the DDR3 (external run at??)

 

Basically, what i dont understand yet, is why do i need to use the PL? (its a better solution i guess yes but im just trying to understand the limitations of the system)

0 Kudos
Scholar austin
Scholar
6,845 Views
Registered: ‎02-27-2008

Re: ZYNQ on zedboard interfacing DS26518

Jump to solution

b,

 

I am trying to suggest the simplest, and most likely to work scenario.  I am sure many other scenarios will also work, it is just thet they may be harder to implement.

 

I belive xapp1028 is a bare metal/linux example applications note (I think I have got the number right, you can look on zedboard where I posted that that applications note was available (or on the forums).


With all the opitons:  high performance port, regular performance port, gpio, acp port, using bram, or using OCM, there are at least a million ways to configure what you want to do.  Which is best?  I have no idea.

 

But, if you wish to run linux on one cpu, you had better have some other resources for the E1 sampling, as linux may suck up everything, and leave you hanging.  As it is, using linux to move data to the lan has to be done carefully, as it may get into a state evry so often where it lags behind the traffic (linux is not a real-time OS).

 

Having the system simple, is always a good thing.  For example, using a PS DMAC (DMA controller) to transfer the memory is probably also the best solution, regardless of where the data is.

 

If you wered making your own SoC ASIC, you would have to answer all these questions before tape-out.  With Zynq, you don't need to wait (and wait, and wait) and then have to throw the masks out, and start over again.  The bitstream takes care of the custom part (and  can be changed often,a nd easily).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
Visitor badmanjoe
Visitor
6,839 Views
Registered: ‎05-10-2013

Re: ZYNQ on zedboard interfacing DS26518

Jump to solution

Thank you Austin! This has been very helpful to me.

you probable ment xapp1026

0 Kudos
Scholar austin
Scholar
2,426 Views
Registered: ‎02-27-2008

Re: ZYNQ on zedboard interfacing DS26518

Jump to solution

Yes,

 

Thanks for the correction,

 

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
Visitor badmanjoe
Visitor
2,426 Views
Registered: ‎05-10-2013

Re: ZYNQ on zedboard interfacing DS26518

Jump to solution

1078***

0 Kudos