Zedboard Zynq error AXI DMA SgIntErr and lwip UDP

[l.sara_tg]

Dear all,

I would like to use Zedboard  Evaluation Board 7z020 in order to send lots of bytes over Gigabit Ethernet (bare metal system).

The PS should receive bytes from PL through AXI DMA Rx  interrupt and then it should transfer them over GbE.

DMA SG Stream to MM occurs every 20ms and transfer 32Byte of data to PS.

My firts attempt, which was working well, was the following

• PS receives interrupt, copies the received bytes and send a small UDP packet ( which size was 1024 Byte) to a remote Ethernet client.

I have then modified lwip configuration in order to maximize throughput, following the configuration described in last two pictures of the following link:

http://www.wiki.xilinx.com/Zynq-7000+AP+SoC+Performance+%E2%80%93+Gigabit+Ethernet+achieving+the+best+performance

Now  I can transfer a big packet of 65KB, but DMA doesn’t  work anymore.

I read the following errors:

Dump registers 40400030:

Control REG: 00017002

Status REG: 00010109

Cur BD REG: 00FB78C0

Tail BD REG: 0110FFC0

The following pictures shows memory status after DMA initialization. When first interrupt occurs, no data is copied at register 0x00FC19C0.

Where is the problem? Can yuo help me?

Thanks very much

Best regards

Sara

[l.sara_tg · Accepted solution]

Hello,

I resolved my problem closing Vivado and SDK software, and lunching them again .

Bye

[jeremy.shepard]

Hi,

Can you share your code for the DMA to UDP packet that you got to work properly?

[bbhatt]

Can you please share your code with us? Thank you.