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Registered: ‎04-18-2018

Zynq: AXI Ehernet Subsystem with MII2RMII problem

Hello, guys

We have been applying pl ethernet of zynq-7020 design in my custom zynq board. We are using Axi Ethernet Subsystem(7.1) with MII interface, linked with MII to RMII(2.0) IP, connected to onboard RMII interfaced phy.


All links between IPs are auto connected. But after running implementation, we get critical warnings:



The first 4 warnings come from Ethernet Subsystem IP internal constraint, which I can't modify, someting related to MII rx_clk in file "bd_929b_mac_0_clocks.xdc":

# Define data valid window with respect to the clock.
# The spec states that, worst case, the data is valid 10 ns before the clock edge.
# The worst case it to provide 10 ns hold time (a 20 ns window in total)
set_input_delay -clock $rx_clk -max 30            [get_ports {mii_rxd[*] mii_rx_er mii_rx_dv}]
set_input_delay -clock $rx_clk -min 10 -add_delay [get_ports {mii_rxd[*] mii_rx_er mii_rx_dv}]


And last 12 warnings came from MII interface, which are connected to MII to RMII IP directly. Yet I am not sure it is right changing IOB property from TRUE to FALSE.


These warnings are very confusing to me, cause I didnot do much self defined design yet. Is there something special I'm missing?


We link gtx_clk of AXI Ehternet from 125MHz generated from ZYNQ7 Processing System(FCLK_CLK2). 

We link ref_clk of MII2RMII from 50MHz generated form ZYNQ7 Processing System(FCLK_CLK3), also exported to external phy.



We are using Vivado 2017.4, and Linux side is all right(Mac and Phy were founded) but failed to ping. We think it's related to these critical warnings.


Any idea why? Is that a version related bug? Thank you for your help.

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