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Adventurer
Adventurer
200 Views
Registered: ‎10-12-2018

Zynq US+ Address Mapping to AXI

Hi to All,

I want to discover the PL-PS AXI address mapping to the DDR4 controller address lines, the bank groups, banks, rows, and so on. My device is Zynq US+ MPSoC.

How can I obtain that?

Amir

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Xilinx Employee
Xilinx Employee
164 Views
Registered: ‎01-09-2019

Re: Zynq US+ Address Mapping to AXI

Hello @amir.massah 

Have you seen the Register Reference?  https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html

If you search for DDR4 or DDRC that should pull up the controller's registers.

The TRM might also hold the information you want (page 1057 has PL-PS boundary specifics for FPD): https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf

Thanks,

Caleb

Thanks,
Caleb
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