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Visitor cor
Registered: ‎07-01-2018

Zynq ultrascale+ clocking


I'm new to the Zynq Ultrascale family. And I'm a bit confused about how to clock the PL stuff.

The PS can generate 4 clocks. Is this mend to clock all kind of PL stuff? Or is this mainly mend for the axi busses?


I need for instance a low jitter 200MHz clock for MIPI interfaces. Can I use the PS clocking system for that? Or is that not the way to go and should I use an external oscillator connected to the FPGA and use a PLL or MMCM to generate this clock?

If so, what are the clock inputs to use? I do not see dedicated clock inputs.


And how to generate a general purpose 150MHz PL clock without jitter requirements. Using the PS output clocks for this is fine?



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