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938 Views
Registered: ‎02-18-2018

Zynq7000 internal memory structure and configuration process details

Hello,

 

I'd like to use Zynq7020, but since the project is of high reliability nature,

I'd like to configure the device from a voting SPI memory module. The

module will be composed of 3 identical copies of the configuration stream

in separate chips and a majority gate will be used to select the bit value.

There are two questions:

 

1. Does the Zynq chip contain any stored charge circuits which can loose their

content or is it purely RAM based?

 

2. The configuartion interface supported by Zynq is QSPI, but using the entire

four lines would require to replicate the voting engine four times. Also, the DIN line

in x2+ modes is bidirectional, which complicates the voter even more. On the other

hand, QSPI must start in x1 mode and the legacy SPI protocol makes the voter

simple, a single 8:1 MUX like the 74AC251 would be enough to do the job. So,

is there a way to keep the bootloader in x1 mode for the entire configuration process?

I don't care about the configuration speed, the reliability is critical.

 

 

 

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Xilinx Employee
Xilinx Employee
915 Views
Registered: ‎01-10-2012

Re: Zynq7000 internal memory structure and configuration process details

Hi @piotr.wyderski

This post could have been posted to Embedded Processor System Design for better response.

My  quick inputs

1. If its a query w.r.t to Zynq  PL block configuration memory type, its SRAM based memory.

2. I would leave it to embedded expert to comment, but i think QSPI x1 boot loading should be possible.

 

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901 Views
Registered: ‎02-18-2018

Re: Zynq7000 internal memory structure and configuration process details

Hi Gurupra,

 

feel free to move this post to a better place if at all possible, no problem.

 

Ad 1: The confusing statement is "On-chip boot ROM" from DS190. This

is the program that loads the first stage bootloader etc. Is it flash or

mask-programmed?

 

Ad 2: many independent sources seem to confirm your opinion, which

is good, because it would make the voter's implementation dead-simple.

 

    Best regards

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Xilinx Employee
Xilinx Employee
886 Views
Registered: ‎01-10-2012

Re: Zynq7000 internal memory structure and configuration process details

Hi @piotr.wyderski

 

1, Yes there is a small piece of inbuilt non volatile ROM in PS used for boot loading, this can't be altered nor user alterable.

 

 

Shall ask our moderator to move this post to embedded.

 

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883 Views
Registered: ‎02-18-2018

Re: Zynq7000 internal memory structure and configuration process details

Gurupra,

 

but is this a true ROM (hardcoded) or a factory-programmable flash? Is it subject to loosing its content over (very) long time?

 

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Xilinx Employee
Xilinx Employee
873 Views
Registered: ‎01-10-2012

Re: Zynq7000 internal memory structure and configuration process details

Hi @piotr.wyderski

Its hard coded. Any ARM processor (other generic processors too) will have this very small footprint ROM to get the device boot up after power on and load the subsequent boot image based on user settings(QSPI/SD etc).