UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor nitron
Visitor
606 Views
Registered: ‎01-11-2019

Zynq7020 Critical Section code

Jump to solution

Hi,

On a Zynq 7020 (Cortex A9) I have some critical section code.

By critical section I mean a section of code that should not be interrupted by any ISR.

So  before entering the critical section code I disable all the interrupts and after the critical code is executed I enable them afterwards like this:

Xil_ExceptionDisable()

// execute critical code, 5-10 lines of basic code so very short in time

Xil_ExceptionEnable()

The problem is that sometimes some interrupts are missed so I wonder:

1. If an interrupt is triggered during the critical code execution then the interrupt is it serviced just after Xil_ExceptionEnable() (the desired behavior) or it disapears forever in the darkness ?

2. What is the standard way of entering and leaving a critical section code ? Can anyone share a code example?

 

Thank You for your answers!

Regards,

0 Kudos
1 Solution

Accepted Solutions
Scholar ericv
Scholar
496 Views
Registered: ‎04-13-2015

Re: Zynq7020 Critical Section code

Jump to solution

@nitron

the procedure you are using is perfectly OK as a mechanism to protect a shared variable in your application. And yes, what @xilinxacct refers to is better because interrupts are not disabled.  When interrupts are disabled / enabled on the A9 through the CPSR register (this is what Xil_ExceptionDisable / Xil_ExceptionEnable do) then when an interrupt occurs during the disabling it remains pending until the interrupts are enabled and it then get procesed.

Is it possible your CPU interrupt takes some times more time to perform the processing than the rate of the interrupts?

If so, there could be a latency build-up so once in a while an interrupt would be missed..

5 Replies
Teacher xilinxacct
Teacher
535 Views
Registered: ‎10-23-2018

Re: Zynq7020 Critical Section code

Jump to solution

@nitron

When you say 'critical section' are you trying to protect a shared variable OR maintain some explicit instruction completion time? Of course, if neither, interrupts are saving and restoring their state, so 'maybe' you don't need it (depending on what you mean).

Knowing what 'you' mean by 'critical section', may help a more specific answer.

0 Kudos
Visitor nitron
Visitor
530 Views
Registered: ‎01-11-2019

Re: Zynq7020 Critical Section code

Jump to solution

Hi,

Thank you for your answer.

By critical section code I mean a code section where I want to protect the access to a shared variable.

One more detail: I have a bare metal application with only one computation intensive interrupt and a backgound task (infinite loop, low priority). The interrupt occurs at very regular intervals. I see spurious interrupts missing (maybe one in a million or even less often).

I have some status register that can be modified both by an interrupt and the infinite loop routines (background, low priority tasks).

When I modify this status register in a low priority task (infinite loop) before altering the content of the register, I disable the interrupts in order to avoid any possible content corruption of the register from an interrupt popping up just in the middle of the low priority task processing.

I know there are other ways of protecting a variable access than disabling all the interrupts during access.

My real concern is that I see missing interrupts so I am not sure that the procedure I am using to disable interrupts are the correct one or I am missing something that leads to interrupt loss.

I must say that the interrupts remain disabled for a very short time (4-5 simple lines of code like setting/resetting bits in different status registers). So the non-interruptible code section cannot take too long in order to hinder the interrupt occurrence.

The processor load is about 30% so the interrupt loss is not caused neither by an processing overload.

At this stage my only clue is that maybe I am doing something wrong with the interrupt disabling procedure and if an interrupt event occurs during the very short window when the interrupts are disabled then the interrupt is not serviced after the interrupts are enabled (the interrupt is lost).

That's why I am asking if my way of disabling and enabling interrupts is OK.

Best Regards, 

 

0 Kudos
Teacher xilinxacct
Teacher
526 Views
Registered: ‎10-23-2018

Re: Zynq7020 Critical Section code

Jump to solution

@nitron

If your interrupt & background task in on the ARM, take a look here, and see if it helps ... https://stackoverflow.com/questions/51795537/critical-sections-in-arm

Use atomics if you can.

If in PL, look at the Mutex IP, and see if you can utilize that.

Hope that helps

If so, please mark as 'solution accepted'

 

 

 

Scholar ericv
Scholar
497 Views
Registered: ‎04-13-2015

Re: Zynq7020 Critical Section code

Jump to solution

@nitron

the procedure you are using is perfectly OK as a mechanism to protect a shared variable in your application. And yes, what @xilinxacct refers to is better because interrupts are not disabled.  When interrupts are disabled / enabled on the A9 through the CPSR register (this is what Xil_ExceptionDisable / Xil_ExceptionEnable do) then when an interrupt occurs during the disabling it remains pending until the interrupts are enabled and it then get procesed.

Is it possible your CPU interrupt takes some times more time to perform the processing than the rate of the interrupts?

If so, there could be a latency build-up so once in a while an interrupt would be missed..

Visitor nitron
Visitor
473 Views
Registered: ‎01-11-2019

Re: Zynq7020 Critical Section code

Jump to solution

Thank you guys for your answers!

@ericvYour answer confirms that the way I disable and enable interrupts cannot be the cause of interrupts missing. I'll wait some time in order to potentially have other (potentially divergent) opinions and if not I'll mark your answer as accepted solution.

Regarding your question: Is it possible your CPU interrupt takes some times more time to perform the processing than the rate of the interrupts?

The interrupt occurs every 50us. I see that once in a while one interrupt is missing since I monitor the time elapsed between two consecutive interrupt entry points. This time doubles when one interrupt is missing. 

From what I know (I measured) the maximum time the interrupts takes is about 19us (regularly 15us). So it seems this is not a problem of processor overload. As I said i have only one interrupt in the system in order to increase determinism so it is only this interrupt that determines the processor load.

I'll look further to other possible (unknown) causes.

@xilinxacctThank you for your answer. I was aware about the stackoverflow thread but not about Mutex IP in PL. I'll give them a look after hopefully the problem with losing interrupts is solved.

 

Regards,

0 Kudos