12-29-2015 10:16 AM
I ran into this error message:
"This peripheral is limited to a fixed base Address of 0x00000000 [512M]. The LSBs of its assigned address must match this base offset. 0x80000000 [512M] violates this restriction. Choose an offset whose LSBs match 0x00000000."
I am trying to map an AXI Fifo into the HP ports so I could write to DDR; based on the Zynq TRM, OCM can be in one of several addresses after reconfiguration (iirc, you have to remap the OCM to get a contiguous OCM address range).
Why can't I remap this peripheral to any of the DDR memory addresses? I think there's something going on here I am missing.
12-29-2015 07:46 PM
just to understand your system a little bit more, why do you have a data fifo between HP interface and S_AXI interface?
12-29-2015 11:08 PM
This was just a test; the rest of the system is empty (for now). In the final system I'd like to read from the DDR memory into a FIFO, and have the FIFO issue a request for more data when it has available space, as it is a video pipeline.
To do that I was going to hack apart the AXI Fifo Generator core to give it a native interface on one side and AXI on the other, and add some control logic.
It looked like the Virtual FIFO controller does something similar, but I don't understand how it is setup (yet).
02-03-2016 12:46 PM
I'm seeing this same error as well. I'm following the CDMA example design shown in chapter 5 of UG1165.
I have an AXI CDMA block attached to the AXI_HP0 and AXI_HP2 ports on my PS via an interconect (see attached). Per the example, I want to have two 256MB buffers in DDR accessible to the CDMA block, located at 0x2000_0000 and 0x3000_0000, respectively. Placing HP2 at 0x3000_0000 violates this 512MB boundary rule (see attached), and I would very much like more control of my address choice than that.
02-08-2016 03:12 PM
Is there anybody who got solved this problem?
I have a same problem during designing to test CDMA.
UG1165 tutorial seems working but, I cannot assign address like 0x1000_0000, 0x2000_0000, or 0x3000_0000.
Is the tutorial wrong? or Vivado's bugs?
02-10-2016 11:47 PM
I was suffered from same issue.
In my case, I modify the DDR Configuration in ZYNQ7 Processing System Block.
I fristly use the Xc7z020clg484-1 preset, at the first made project.
I did not recognize the difference between Xc7z020clg484-1 and ZYNQ 7 EVM board preset.
but, I can find the difference of the DDR Configuration between Xc7z020clg484-1 and ZYNQ 7 EVM board preset by comparing one by one.
I hope my reply can help you.