01-31-2018 04:42 AM
I am working with the ZC706 eval board using the ARM zynq. I have implemented a processing system in a core and it is defined with different entries: both of them as registers. The idea is to change these values without sinthetize and implement the desing in each modification. My question is how could I define these two registers inside the ARM and connect both to the core?
Any suggestion will be appreciated.
thanks in advance
01-31-2018 05:00 AM
01-31-2018 05:11 AM
thank you for your response. Here is attached the picture. Register1 and register2 are two constant entries for the core that configure operations. If I change the value, I need to implement a new design. I would like to define thes values into an ARM memory and it would be connected to the core. I could modify these two values without any change in hardware design. Do you have any suggestion on how I could design it for the virtex7 ARM ZC706?
01-31-2018 06:15 AM
@carloscruz Oh now I get it. Let's see if I can help here.
This document UG1119 is a tutorial on how to package your custom IP
In your case, I suggest you expose these registers as AXI lite. Which is actually very easy to do with the package-IP wizard (above).
Check out this video I did some time ago exactly on how to do that:
01-31-2018 07:08 AM
thank you for your response. I know how to add new logic to my existing design but it is not what I would like to do.
Once my logic is added, I would like to connect my two entries to registers
01-31-2018 07:32 AM
@carloscruz What exactly do you call "registers"? ARM Registers?
You can expose your custom IP logic to the ARM as registers through AXI lite.
02-01-2018 12:17 AM
Hi Henrique, thank you for your response. It is clear now. One my custom IP logic is connected to the ARM as registers through AXI lite, this to registers could be modified. I really don´t know how could it be modified, through SDK?
Sorry for my background in hardware design; all your suggestion are wellcome. I really appreciate it
02-01-2018 01:13 AM - edited 02-01-2018 01:18 AM
@carloscruz If it is through AXI lite then it will behave as memory. In Vivado address editor you can assign an address to your component - or have it auto assigned. From ARM you just need to write into these 32 bits registers as if you were filing a normal variable. H LS would even create a SDK wrapper for you but as this is Custom IP then you have to come up with helpers on your own.
02-01-2018 03:43 AM
Thank you. I have designed my custom IP and I have followed your video in order to import my IP to my global project throught the block diagram. I really don´t know how to connect these two entries through AXI lite in this block diagram. If I solve it, Do you know how to write these 32 bits two registers into ARM as normal variable?
Henrique , I would like to give thanks for all your time and suggestions.
02-01-2018 03:59 AM
You can use Xil_Out32(), which is just basically
volatile u32* regs = (u32*)AXI_ADDRESS_XXX; // From address editor regs = 0x8283; // your value regs = 0x3929; // another value
02-01-2018 06:37 AM
Thanks a lot Henrique, jast a question: If I use a AXI Interconnect to connect a peripherals with an AXI4-Lite connection it makes the connection between the AXI-interconnect of the Zynq and AXI Interconnect of my peripherals an AXI4-Memory mapped connection. I have attached a picture of my core (c_accum_top) were escal and escal2 are the two registers that need to be connected to AXI-lite. In this case, Do I need to connect both to axi_cpu_interconnect or do I need make escal and escal2 external?
02-01-2018 06:53 AM
@carloscruz Is this HLS? If so, you need to tag the arguments as axi lite with
#pragma HLS interface s_axilite port=return bundle=DATA #pragma HLS interface s_axilite port=input bundle=DATA #pragma HLS interface s_axilite port=escal bundle=DATA #pragma HLS interface s_axilite port=escal2 bundle=DATA #pragma HLS interface s_axilite port=output bundle=DATA
02-01-2018 07:15 AM
It is not a HLS design.
The picture shows a part of the princial project block diagram. Apologize I am not familiar with your code written in c for HLS
My core was designed in VHDL and was imported by vivado into the block diagram. Do you know any tutorial or example to solve my problem?
02-01-2018 07:40 AM
02-01-2018 08:06 AM
@carloscruz Well if you follow that video, I explain how to use the package tool to create a sample of AXI Lite that you can use to insert your IP inside. It is a one point intervention, very easy to do. Then you got an AXI lite interface you can easily configure from PS.
Another option would be to use AXI GPIO to interface with your IP. It is easier.
This tutorial uses GPIO to interface with LEDs.
02-02-2018 12:45 AM
thank you for all your comments, I understand better right now. I also need to import an external digital signal to this core. In this case, I will select this signal as peripheral, right? As I am using the ZC706, this evaluation board has GTX TX&RX external SMAs for differential user clock input. My question is if I could use this board input and how I could set an external signal on it. After this question,you have solved this threat and I really appreciate your support as I believe you have helped a lot of followers with your suggestions. Thanks
02-02-2018 12:55 AM
@carloscruz You should really have distinct questions into separate threads. This forum is about knowledge building and Organizing content helps others later with the same doubts find the correct solution.
02-06-2018 05:15 AM
Hi, I solved it. The complete design with my core included has been syntetized, implemented and the bit file has been generated. The two registers (escal, escal2) from my IP core were defined as external ports. I have a feeling that I am mixing the data and control paths. And I would need to have a separate AXI Lite interface for the registers, connected to the cpu_interconnect. here is attached my generated code. Do you think that reg1 and reg2 need to be internal registers in the IP?