05-30-2018 08:46 AM
I am trying to compile a kernel with the --profile_kernel data:all:all:all flag but it fails. If I remove this flag the program compiles and it runs fine. But I need to profile the kernel in order to understand how to improve its performance. I am using these two commands to compile:
xocc -c -t hw --platform zed -g src/aes.cl xocc -t hw -l --profile_kernel data:all:all:all --sys_config ocl a.xo -f zed
As you can see I have one kernel and the platform used is the ZedBoard. The kernel is using OpenCL, I have read the optimization guide and I haven't found anything similar to the error I am getting:
#----------------------------------------------------------- # Vivado v2018.1 (64-bit) # SW Build 2188600 on Wed Apr 4 18:39:19 MDT 2018 # IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 # Start of session at: Wed May 30 17:34:40 2018 # Process ID: 3276 # Current directory: ~/Xilinx/SDSoC_Examples/ocl/getting_started/aes_ocl/_xocc_link_a_bin.dir/_vpl/ipi # Command line: vivado -mode batch -notrace -source ~/Xilinx/SDSoC_Examples/ocl/getting_started/aes_ocl/_xocc_link_a_bin.dir/_vpl/ipi/ipirun.tcl -messageDb ~/Xilinx/SDSoC_Examples/ocl/getting_started/aes_ocl/_xocc_link_a_bin.dir/_vpl/ipi/vivado.pb # Log file: ~/Xilinx/SDSoC_Examples/ocl/getting_started/aes_ocl/_xocc_link_a_bin.dir/_vpl/ipi/vivado.log # Journal file: ~/Xilinx/SDSoC_Examples/ocl/getting_started/aes_ocl/_xocc_link_a_bin.dir/_vpl/ipi/vivado.jou #----------------------------------------------------------- source ~/Xilinx/SDSoC_Examples/ocl/getting_started/aes_ocl/_xocc_link_a_bin.dir/_vpl/ipi/ipirun.tcl -notrace Creating Vivado project and starting FPGA synthesis. --- DEBUG: source ./.local_dsa/prj/rebuild.tcl to create syn project INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.1/data/ip'. INFO: Project created:syn --- DEBUG: setting ip_repo_paths: ~/Xilinx/SDSoC_Examples/ocl/getting_started/aes_ocl/_xocc_link_a_bin.dir/impl/kernels/ip_repo/xilinx_com_hls_aes_1_0 /opt/Xilinx/SDx/2018.1/data/cache/xilinx ./.local_dsa/ipcache /opt/Xilinx/SDx/2018.1/data/ip/xilinx --- DEBUG: update_ip_catalog INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '~/Xilinx/SDSoC_Examples/ocl/getting_started/aes_ocl/_xocc_link_a_bin.dir/impl/kernels/ip_repo/xilinx_com_hls_aes_1_0'. INFO: [IP_Flow 19-1700] Loaded user IP repository '/opt/Xilinx/SDx/2018.1/data/cache/xilinx'. INFO: [IP_Flow 19-1700] Loaded user IP repository '~/Xilinx/SDSoC_Examples/ocl/getting_started/aes_ocl/_xocc_link_a_bin.dir/_vpl/ipi/.local_dsa/ipcache'. INFO: [IP_Flow 19-1700] Loaded user IP repository '/opt/Xilinx/SDx/2018.1/data/ip/xilinx'. --- DEBUG: open_bd_design -auto_upgrade [get_files zed.bd] Adding cell -- xilinx.com:ip:processing_system7:5.5 - ps7 Adding cell -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0 Adding cell -- xilinx.com:ip:clk_wiz:6.0 - clk_wiz_0 Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_0 Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_1 Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_2 Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_3 Successfully read diagram <zed> from BD file <~/Xilinx/SDSoC_Examples/ocl/getting_started/aes_ocl/_xocc_link_a_bin.dir/_vpl/ipi/syn/syn.srcs/sources_1/bd/zed/zed.bd> --- DEBUG: source ./dr.bd.tcl WARNING: [Coretcl 2-1042] No IP was identified for upgrade. WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'STRATEGY' from '0' to '2' has been ignored for IP 'axi_ic_ps7_M_AXI_GP0' WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'STRATEGY' from '0' to '2' has been ignored for IP 'axi_ic_ps7_S_AXI_ACP' WARNING: [BD 41-1306] The connection to interface pin /axi_ic_ps7_S_AXI_ACP/S00_AXI_arcache is being overridden by the user. This pin will not be connected as a part of interface connection S00_AXI WARNING: [BD 41-1306] The connection to interface pin /axi_ic_ps7_S_AXI_ACP/S00_AXI_awcache is being overridden by the user. This pin will not be connected as a part of interface connection S00_AXI --- DEBUG: save_bd_design Wrote : <~/Xilinx/SDSoC_Examples/ocl/getting_started/aes_ocl/_xocc_link_a_bin.dir/_vpl/ipi/syn/syn.srcs/sources_1/bd/zed/zed.bd> --- DEBUG: inserting profiling cores --- DEBUG: Adding profiling of host and kernel masters... --- DEBUG first CU slot : /aes_1 --- DEBUG Axilite CU bd net : /axi_ic_ps7_M_AXI_GP0_M00_AXI --- DEBUG Axilite CU Interconnect : /axi_ic_ps7_M_AXI_GP0 --- WARNING: Unable to find host master to profile... --- DEBUG: inserting SystemILA debug cores --- DEBUG: insert_chipscope_debug: No chipscope_debugs dict name - nothing to insert --- DEBUG: assign_bd_address </ps7/S_AXI_ACP/ACP_DDR_LOWOCM> is being mapped into </aes_1/Data_m_axi_gmem> at <0x00000000 [ 512M ]> </ps7/S_AXI_ACP/ACP_QSPI_LINEAR> is being mapped into </aes_1/Data_m_axi_gmem> at <0xFC000000 [ 16M ]> </ps7/S_AXI_ACP/ACP_IOP> is being mapped into </aes_1/Data_m_axi_gmem> at <0xE0000000 [ 4M ]> INFO: [BD 41-1051] The usage <register> of peripheral </ps7/S_AXI_ACP/ACP_IOP> does not match the usage <memory> of master </aes_1/Data_m_axi_gmem> and will be excluded using sparse connectivity from its address space. Use the include_bd_addr_seg command to override this precaution and make this peripheral visible within this masters address space. Excluding </ps7/S_AXI_ACP/ACP_IOP> from </aes_1/Data_m_axi_gmem> </ps7/S_AXI_ACP/ACP_M_AXI_GP0> is being mapped into </aes_1/Data_m_axi_gmem> at <0x40000000 [ 1G ]> INFO: [BD 41-1051] The usage <register> of peripheral </ps7/S_AXI_ACP/ACP_M_AXI_GP0> does not match the usage <memory> of master </aes_1/Data_m_axi_gmem> and will be excluded using sparse connectivity from its address space. Use the include_bd_addr_seg command to override this precaution and make this peripheral visible within this masters address space. Excluding </ps7/S_AXI_ACP/ACP_M_AXI_GP0> from </aes_1/Data_m_axi_gmem> --- DEBUG: validate_bd_design -force ERROR: [BD 41-1811] The interconnect </axi_ic_ps7_M_AXI_GP0> is missing a valid master Interface connection ERROR: [Common 17-39] 'validate_bd_design' failed due to earlier errors. while executing "validate_bd_design -force" (procedure "ocl_util::init_ocl_project_unip" line 212) invoked from within "ocl_util::init_ocl_project_unip $dsa_info $config_info $clk_info $debug_profile_info" (file "~/Xilinx/SDSoC_Examples/ocl/getting_started/aes_ocl/_xocc_link_a_bin.dir/_vpl/ipi/ipirun.tcl" line 168) INFO: [Common 17-206] Exiting Vivado at Wed May 30 17:34:57 2018...
I am new to FPGA development, so it might be something obvious...
06-06-2018 12:26 PM
Hi mompes,
I think it would be recommended to not try and use an openCL kernel with sdsoc such as with a ZED. You should try sticking with the GUI flow on just taking a function from your design and choosing it to be pushed onto Hardware. The reason is that you will take a hit on the added overhead for the openCL memory setup.
xocc and the --profile_kernel really makes the most sense for the SDAccel flow moreso then the SDSOC flow. I suspect the issue you are running into is that the zed platform isn't setup like a SDAccel DSA for the profilinf run.