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Participant
Participant
809 Views
Registered: ‎09-02-2016

SDAccel RTL kernel example mistake: +2 instead of +1

Hi, 

 

I have set up ADM-PCIE-8K5 to run the RTL kernel example generated from SDAccel 2017.2. I directly implement the example code generated from Xilin -> Create RTL kernel ...  without any changes. This example reads 16K memory data, each with 32 bits. It adds one to each data and then send back to the exact location.

The HW emulation shows the correct results (adding one to each data unit).

However, the system run gives incorrect results: adding two to each data unit. The error message is shown below:

ERROR in rtl_design - array index 0 (host addr 0x000) - input=0 (0x0), output=2 (0x2)
ERROR in rtl_design - array index 1 (host addr 0x004) - input=1 (0x1), output=3 (0x3)
ERROR in rtl_design - array index 2 (host addr 0x008) - input=2 (0x2), output=4 (0x4)
ERROR in rtl_design - array index 3 (host addr 0x00c) - input=3 (0x3), output=5 (0x5)
ERROR in rtl_design - array index 4 (host addr 0x010) - input=4 (0x4), output=6 (0x6)
ERROR in rtl_design - array index 5 (host addr 0x014) - input=5 (0x5), output=7 (0x7)
ERROR in rtl_design - array index 6 (host addr 0x018) - input=6 (0x6), output=8 (0x8)


...

ERROR in rtl_design - array index 4092 (host addr 0x3ff0) - input=4092 (0xffc), output=4094 (0xffe)
ERROR in rtl_design - array index 4093 (host addr 0x3ff4) - input=4093 (0xffd), output=4095 (0xfff)
ERROR in rtl_design - array index 4094 (host addr 0x3ff8) - input=4094 (0xffe), output=4096 (0x1000)
ERROR in rtl_design - array index 4095 (host addr 0x3ffc) - input=4095 (0xfff), output=4097 (0x1001)

 

I have run the open-cl example VADD and the result is correct so I think the board has been correctly setup. The sources used in the test have been attached in the attachment.

Can anybody help with this problem?

 

 

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Xilinx Employee
Xilinx Employee
770 Views
Registered: ‎06-17-2008

Hi @gkillua36,

I took a look at your kernel RTL code. It looks like you modified the constant from 1 to 100. I am curious what is the harware output under this scenario? Also, have you tried this design on other boards(if any) as well?

 

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Participant
Participant
766 Views
Registered: ‎09-02-2016

Hi @yunl,

 

Thanks for the reply. Actually I test both the case of constant 1 and 100. For the case +100, the result is +200. 

I do not have other boards so I cannot test on another platform. But the hardware emulation can pass through.

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Xilinx Employee
Xilinx Employee
747 Views
Registered: ‎06-17-2008

Hi @gkillua36,

Could you try setting m00_axi interface's data width to '4 bytes' intead of the default '64 bytes' and see how it goes?

 

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Participant
Participant
736 Views
Registered: ‎09-02-2016

Hi @yunl,

 

Setting to 4 bytes can pass the test. Do you see any problem from this?

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Xilinx Employee
Xilinx Employee
727 Views
Registered: ‎06-17-2008

Hi @gkillua36,

Actually I am not aware of any known issues and I didn't find any problems in the RTL code. It's just from your observations, I doubted the problem is occured during DDR accesses, either on host-DDR or kernel-DDR. As in the main.c file, int type data is used to create the buffer, therefore I asked you to modify the kernel's AXI master interface width to 32-bit as well as a trial. Since there are limited debugging methods in 17.2, I think it may be difficult to locate the root cause.

 

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