04-19-2019 09:15 AM - edited 04-19-2019 10:03 AM
I'm pretty new to OpenCL and the RTL kernel architecture. I am trying to develop a kernel that does a lot of indipendant communication with multiple input/output ques, along with writing to a BRAM block.
In my system I require a a que from the host to a block in the kernel and another que from the block back to the host.
Additionally, I need to write and read a BRAM block inside the kernel.
My question is, will I need an AXI interface for each que and BRAM block? Like in the RTL kernel example in the SDAccel user guide(UG1023) they implement m00_axi and m01_axi.
My second question is, can I utilize both ports of the Dual port RAM AND write and read the information from the host?
Attached is the architecture I'm trying to achieve.
06-19-2019 04:02 AM - edited 06-19-2019 04:03 AM
For streaming data from/to host, you may choose streaming in 2019.1 , for example: https://github.com/Xilinx/SDAccel_Examples/tree/master/getting_started/host/streaming_host_bandwidth
Fou random access Memory, you still need to choose DDR or PLRAM or HBM, depending on the platform and memory size.