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Observer
Observer
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Registered: ‎09-12-2018

opencl RTL kernel with multiple axi interfaces

Hi there,

I'm pretty new to OpenCL and the RTL kernel architecture. I am trying to develop a kernel that does a lot of indipendant communication with multiple input/output ques, along with writing to a BRAM block.

In my system I require a a que from the host to a block in the kernel and another que from the block back to the host.

Additionally, I need to write and read a BRAM block inside the kernel.

My question is, will I need an AXI interface for each que and BRAM block? Like in the RTL kernel example in the SDAccel user guide(UG1023) they implement m00_axi and m01_axi.

My second question is, can I utilize both ports of the Dual port RAM AND write and read the information from the host?

Attached is the architecture I'm trying to achieve.

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Xilinx Employee
Xilinx Employee
545 Views
Registered: ‎03-24-2010

For streaming data from/to host, you may choose streaming in 2019.1 , for example: https://github.com/Xilinx/SDAccel_Examples/tree/master/getting_started/host/streaming_host_bandwidth

Fou random access Memory, you still need to choose DDR or PLRAM or HBM, depending on the platform and memory size. 

Regards,
brucey
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