11-29-2018 07:46 PM - edited 11-30-2018 12:46 AM
Hi , all. I have got a problem when using kcu1500 to accelerate kernels.
Problem: I have a C kernel and want to run at 300MHz, but the hls always gives the critical path (as below)
ap_int<PIX_WIDTH +1> diff0 , diff1
ap_uint<2*PIX_WIDTH> mult_p0 , mult_p1 ;
ap_uint<32> temp_sum ;
diff0 = a0-b0 ;
diff1 = a1-b1 ;
mult_p0 = diff0 * diff0 ;
mult_p1 = diff1 * diff1 ;
temp_sum = mult_p0 + mult_p1;
Estimated clock period (3ns) exceeds the target (target clock period: 3ns, clock uncertainty: 0.4125ns, effective delay budget: 2.5875ns).
WARNING: [SCHED 204-21] The critical path consists of the following:
'sub' operation ('r_V_3', ../code/l2_search/l2_search.cpp:113) (1.97 ns)
'mul' operation ('mult_p0_V', ../code/l2_search/l2_search.cpp:121) (1.03 ns)
And I have tried several kinds of directive and none of them worked, such as :
1- HLS LATENCY DIRECTIVE ： to constraint the minimal subtraction latency to 1 or 2
2- insert diff_temp variables , like " diff = a-b ; diff_r = diff ; mult_p = diff_r * diff_r ;
None of them worked. So, can anybody help me ?
It seems that now matter what target period I set , the Estimated period is always equal as the target, and the clock uncertainty results in timing problem.
12-05-2018 04:51 AM
Hi, @yanhan ,
Do you mean even you set the target period to 4ns, the "Estimated clock period " will also be 4ns?
12-05-2018 06:50 AM - edited 12-05-2018 06:09 PM
@hongh , thanks for you reply.
yes. actually，the utilization(of total resource, not SLR) is not very big and just about 10% lut and 36% DSP used .
only if i set the target period to 5ns, the estimated period would be different.
12-05-2018 06:35 PM
I also have another question .
in some of my design , at beginning, i set --kernel_frequency 300 , the sdaccel told me cannot meet the timing and auto decrease to some frequency, such as 270MHz.
while when i set the same degin to 250MHz, the log also said cannot meet the timing and auto set to , such as 234MHz or 196MHz, 😓
My question is , what results in the problem and is there any document about design rules and design experiences which can lead to hign performance.