04-13-2018 03:59 AM
I'm trying to use SDAccel 2017.1 with my own RTL Kernel.
I used the RTL Kernel Wizard as starting point for the interface generation.
I created all the needed glue logic for transferring data from the FIFO to my RTL Kernel.
I know that my Kernel with previous design(not with SDx) worked up to 200MHz which is below the required 250MHz for the AXI4 interface. So I decided to use two clocks for an asynchronous design and modified accordingly to make the stuffs working in hardware.
My problem is that XOCC didn't find how to link the ap_clk_2 to other wires/clocks.
I checked the Vivado project it created and my IP has two disconnected ports (ap_clk_2 and ap_rst_n_2).
I checked also the SDAccel Repo examples with the example of RTL with two clocks but I didn't really understand where and if exists this option or how the tool links these two ports.
I'm trying to figure out how could I link them automatically, if there are some specific options, if I miss something.
Thank you in advance
04-13-2018 10:33 AM
Can you link the error message xocc gives? And can you explain more about how the clocking is setup? There is a limit on the number of clocks for a kernel in SDAccel.
04-16-2018 01:19 AM
Thank you for the response
ERROR: [XOCC 41-758] The following clock pins are not connected to a valid clock source: /TiReX_v2_1/ap_clk_2
This is the error XOCC returns to me.
I followed the guide of SDAccel and setup the RTL Kernel Wizard to use 2 clocks in my design: 1 standard for the AXI interface and one for my custom Kernel that I know should run at a lower clock frequency (i.e. 130 vs 250 of the AXI).
I used the example design the RTL Wizard outputs. I set the parameter of the number of clocks to 2 which should enable the usage of the async fifo needed for my clock domain.
06-20-2018 06:19 PM
Please refer Xilinx github example "rtl_vadd_2clks":
package_kernel.tcl demonstrated how to associate a clock with its bus interfaces as follows:
ipx::associate_bus_interfaces -busif m_axi_gmem -clock ap_clk [ipx::current_core]
ipx::associate_bus_interfaces -busif s_axi_control -clock ap_clk [ipx::current_core]
ipx::infer_bus_interface ap_clk_2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface ap_rst_n_2 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
The github example associated the 1st clock "ap_clk" with the bus interfaces "s_axi_control" and "m_axi_gmem", and used the 2nd clock "ap_clk_2" to control the kernel, and used following xocc option to control the kernel frequencies:
xocc --kernel_frequency "0:150|1:250"
where "0:150" sets "ap_clk" as 150 MHz, and "1:250" sets "ap_clk_2" as 250 MHz.
For your case, make sure the 2nd clock "ap_clk_2" is used (wired) in your RTL kernel design, use "xocc --kernel_frequency "0:250|1:130" assuming you want "ap_clk" as 250 MHz, and "ap_clk_2" as 130 MHz.
Please note, 2 kernel clock names have to be named as "ap_clk" and "ap_clk_2" respectively in kernel's top module.
08-27-2019 06:27 AM
Trying to run xocc with --kernel_frequency 0:300|1:500 ....
1:500 command not found.
The full xocc command I'm trying to run:
/tools/Xilinx_new/SDx/2019.1/bin/xocc -t hw --platform xilinx_u250_xdma_201830_1 --kernel_frequency 0:300|1:500 --save-temps -l --nk sdx_kernel_wizard_1:1:sdx_kernel_wizard_1_1 --messageDb binary_container_1.mdb --sp sdx_kernel_wizard_1_1.m00_axi:DDR --sp sdx_kernel_wizard_1_1.m01_axi:DDR --sp sdx_kernel_wizard_1_1.m02_axi:DDR --sp sdx_kernel_wizard_1_1.m03_axi:DDR --xp misc:solution_name=link --temp_dir binary_container_1 --report_dir binary_container_1/reports --log_dir binary_container_1/logs --remote_ip_cache /home/moshe/sdx_2019_workspace/ip_cache -o"binary_container_1.xclbin" /tools/programs/sdx/sdx_2019_workspace/try_2019_t1/vivado_rtl_kernel/sdx_kernel_wizard_1_ex/sdx_imports/sdx_kernel_wizard_1.xo
I've chekced that the package_kernel.tcl is updated as shown in the comment above, ap_clk and ap_clk_2..
What can I do?
What may I miss?