UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
546 Views
Registered: ‎07-30-2018

SDLAccel RTL Kernel with slave AXI4 port

Jump to solution

Hi All,

 

I'm porting an existing accellerator card IP core into the SDAccel enviroment.

The issue that I have is that it has a salve AXI4-MM interface for a data port that needs to be conected to the PCIe XDMA engine.It also has an AXI4-MM interface for conection to external memory and hte IP core controles the DDR4 data transfers. The PCIe XDMA is a streaming data interface for a number of job descriptors which a max size of 16K each;

 

I Know that the docs state that all AXI4 interfaces should be masters or streaming, howrver it also implies that an AXI4-MM SLAVE can be used.

 

Has anyone ever done this or know if it is possible. The target platform is theVCU1525 card with default DSA setup, although this may need modifications.

 

Can anyone provide any help with this

 

Thanks

 

Mark N

0 Kudos
1 Solution

Accepted Solutions
636 Views
Registered: ‎07-30-2018

回复: SDLAccel RTL Kernel with slave AXI4 port

Jump to solution

Iris

 

Thanks, so all I need to do is the inclusion of the SRL interconnects on the AXI4 memory mapped interface from the XDAM.

 

This is exactly what I was hoping for.

 

Thanks

 

Mark

0 Kudos
2 Replies
Xilinx Employee
Xilinx Employee
510 Views
Registered: ‎08-02-2007

回复: SDLAccel RTL Kernel with slave AXI4 port

Jump to solution

Mark,

XDMA IP should have Memory Map Interface used as Master port  which can connect with your slave port

regards

Iris

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
637 Views
Registered: ‎07-30-2018

回复: SDLAccel RTL Kernel with slave AXI4 port

Jump to solution

Iris

 

Thanks, so all I need to do is the inclusion of the SRL interconnects on the AXI4 memory mapped interface from the XDAM.

 

This is exactly what I was hoping for.

 

Thanks

 

Mark

0 Kudos