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Explorer
Explorer
395 Views
Registered: ‎05-23-2017

ddr burst read doesn't work, stall happens.

Here is the code for read data from ddr.

Each data point contain 60 D_point_512 structure, i.e. 60x16 ap_fixed<32,8>  data.

After read 60  D_point_512 type of data from the port, I will put all 60x16 data to a structure "feature_or_buffer0" with 960 elements.

 

typedef struct point_512 //for floating/fixfloating point read ,the  data on port
{
    ap_fixed<32,8> x[16];
} D_point_512;

typedef struct point_or //for originla feature vector
{
Dtype_s x[960];
} D_point_or;
void read_feature_or(const D_point_512 *feature_or, Dtype_uint data_size, hls::stream<D_point_or> &feature_or_buffer0 ){ #pragma HLS INLINE off D_point_512 feature_or_temp[60]; #pragma HLS ARRAY_PARTITION variable=feature_or_temp->x complete dim=0 D_point_or feature_or_buffer_temp; #pragma HLS ARRAY_PARTITION variable=feature_or_buffer_temp.x complete dim=0 Dtype_uint loop_num = 60;// each 512 bit including 16 float data read_feature_pca0: for(Dtype_uint i=0; i < data_size; i++){ #pragma HLS LOOP_TRIPCOUNT min=10 max=10 #pragma HLS PIPELINE read_feature_or1: for(Dtype_uint j=0; j<60; j++){ #pragma HLS pipeline II= 1 feature_or_temp[j] = feature_or[i*60+ j]; } read_feature_or2: for(Dtype_uint j=0; j<60; j++){ #pragma HLS pipeline II= 1 //Dtype_uint inter = j*16; Dtype_uint inter = j<<4; read_feature_or3: for(Dtype_uint k=0; k<16; k++){ #pragma HLS unroll feature_or_buffer_temp.x[inter+k] = feature_or_temp[j].x[k]; } } feature_or_buffer0 << feature_or_buffer_temp; } }

 

From the wave-form after the hardware emulation I can see the 60 read from the DDR is not burst and stall happens.

The interval between the two yellow line is a 60 times read.

How to get rid of the stall and burst read the data?

ttty6w.jpg   

An message was generated during the compilation( not sure whether this related to this issue).

INFO: [XFORM 203-811] Inferring multiple bus burst read of a total cumulative length 60 on port 'query_or.x' ( src/pcaf_fpga.cpp:107:2). These data requests might be further partitioned to multiple requests during RTL generation, based on max_read_burst_length or max_write_burst_length settings.

 

 

Thanks.

 

 

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4 Replies
Explorer
Explorer
332 Views
Registered: ‎05-23-2017

Re: ddr burst read doesn't work, stall happens.

From the ug902 I noticed that 

 

When using a for loop to implement burst reads or writes, follow these requirements:
• Pipeline the loop
• Access addresses in increasing order
• Do not place accesses inside a conditional statement
• For nested loops, do not flatten loops, because this inhibits the burst operation

 

For my case the "read_fearture_0r1" loop  is nested in the "read_feature_pca0" loop.

If I pipeline the parent loop, i.e."read_feature_pca0", then the "read_fearture_0r1" loop will be unrolled automatically.

How shoud I resolve this conflict and enable the burst read?

 

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Xilinx Employee
Xilinx Employee
329 Views
Registered: ‎06-17-2008

Re: ddr burst read doesn't work, stall happens.

Have you tried with DATA_PACK pragma? If it is still not working, can you share a simplified test case?

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Explorer
Explorer
308 Views
Registered: ‎05-23-2017

Re: ddr burst read doesn't work, stall happens.

@yunl

Hi Yunl,

 

Thank you very much for you reply.

 

asdfasdf.JPG   

Yes I am using the data_pack pragma on the structure.

Each read from the feature_or port is a 512bit width.

The issue is the readings from this port is not that continuous and there is stall between two reads.

How Can I use burst read?

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Xilinx Employee
Xilinx Employee
287 Views
Registered: ‎06-17-2008

Re: ddr burst read doesn't work, stall happens.

Hi @mathmaxsean,

It would help if you can send me a test case so that I can check it my end. If you are not willing to upload the case here, I can send your personal email an ezmove(secured ftp) link and you may upload the files there.

 

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