07-14-2017 09:13 AM
First of all I checked the other posts related to TCF error in SDSOC 2016.2 but did not seem that any other matched my issue.
I have the following situation: I am using SDSOC 2016.2 to accelerate some functions and I observed that sometimes I get an error message like the one in attachment when I try to accelerate a function. It does not matter which function it is.
Once I remove all the functions that I wanted to accelerate from SDSOC project overview "Hardware functions" section and rebuild the image then I am able to run it successfully on the board.
The error presented is reproduced only when there is some functionality accelerated.
I tried to isolate the issue and simplified the hardware function used for testing in terms that is now a dummy functions which just reads input array and write output array parameter.
Also I reduced the operations performed in the main function as I read that "cannot halt processor core" might mean that the CPU is doing some illegal memory accesses. I really don't see how the code(at least the application) can perform any illegal memory access in the way that I simplified the application now.
Basically I have now a simple main function that allocates memory for some arrays on the heap and then passes that arrays to an accelerated function that does a simple read/write operation on the arrays.
And the issue viewed in the attachment is still reproducible even in that case.
What bothers me the most is the behavior reproduces only if there is some kind of functionality that is accelerated in hardware.
Once all the code is executed in ARM there is no issue. I would very much like to get any kind of hint of why might that happen.
I use ZC706 board and vivado 2016.2 as well.
Thank you in advance for the help!
07-17-2017 02:34 PM
Do you see this issue on a mmult design targetting the zc706 platform? This would rule out any board/pc issues.
When you debug an application in SDx, there is a ps7_init.tcl that is created based on your platform. This is used to configure the ps including any ps to pl clocks, and to reset the AFI (AXI FIFO Interface), and toggle the ps to pl reset amongst other things. If this isnt done properly, then if the processor tries to access the accllerated IP (which is the base address of the hls genrated IP core in the generated Vivado project, then this will fail with the error message you are seeing.
You could do a manual read of the HLS IP from the XSCT (launch this from the sdx shell). connect to the board, and download the bitstream. Then source the ps7_init.tcl, then config the ps (ps_init), reset the AFI (ps7_post_config). Then do a memory read (mrd address).
Also, the SDK log console would be great to see what was going on when this failed.