UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor joe.ye
Visitor
1,110 Views
Registered: ‎09-05-2013

CHaiDNN-How to reduce FPGA resources

Hello Guys,

 

I would like to reduce some FPGA resources for running CHaiDNN on zcu106 platform(not zcu102).

I noticed that  most resources consumed on module xi_convolution_top. So, I tried to change the parameters in xi_conv_config.h.

But, it seems that no impact on resource(LUT, BRAM, DSP, etc).

 

Could you please give me some hints? Thank you in advance.

0 Kudos
2 Replies
Moderator
Moderator
1,022 Views
Registered: ‎09-12-2007

Re: CHaiDNN-How to reduce FPGA resources

What changes did you make to the config file?

0 Kudos
Xilinx Employee
Xilinx Employee
574 Views
Registered: ‎07-25-2018

Re: CHaiDNN-How to reduce FPGA resources

0 Kudos