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Xilinx Employee
Xilinx Employee
4,112 Views
Registered: ‎10-22-2015

Not able to generate hw platform

When I followed the tutorial to build a hw platform, I tried the following code, but it gives the following errors:

 

for {set i 0} {$i<16} {incr i} {sdsoc::pfm_irq $pfm In${i} xlconcat_0}
ERROR: pfm_irq - port 'In0' is not the least significant available port on instance 'xlconcat_0'
ERROR: pfm_irq - port 'In1' is not the least significant available port on instance 'xlconcat_0'
ERROR: pfm_irq - port 'In2' is not the least significant available port on instance 'xlconcat_0'
ERROR: pfm_irq - port 'In3' is not the least significant available port on instance 'xlconcat_0'
ERROR: pfm_irq - port 'In4' is not the least significant available port on instance 'xlconcat_0'
ERROR: pfm_irq - port 'In5' is not the least significant available port on instance 'xlconcat_0'
ERROR: pfm_irq - port 'In6' is not the least significant available port on instance 'xlconcat_0'
ERROR: pfm_irq - port 'In7' is not the least significant available port on instance 'xlconcat_0'
ERROR: pfm_irq - port 'In8' is not the least significant available port on instance 'xlconcat_0'
ERROR: pfm_irq - port 'In9' is not the least significant available port on instance 'xlconcat_0'
ERROR: pfm_irq - port 'In10' is not the least significant available port on instance 'xlconcat_0'
ERROR: pfm_irq - port 'In11' is not the least significant available port on instance 'xlconcat_0'
ERROR: pfm_irq - port 'In12' is not the least significant available port on instance 'xlconcat_0'
ERROR: pfm_irq - port 'In13' is not the least significant available port on instance 'xlconcat_0'
ERROR: pfm_irq - port 'In14' is not the least significant available port on instance 'xlconcat_0'
ERROR: pfm_irq - port 'In15' is not the least significant available port on instance 'xlconcat_0'

 

Not sure why I cannot enable interrupts on PS. Any help?

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2 Replies
Xilinx Employee
Xilinx Employee
4,103 Views
Registered: ‎11-25-2009

Re: Not able to generate hw platform

Make sure the following are true:

1. You have an instance called "xlconcat_0"

2. The value of NUM_PORTS in the block is the same as the number of connected signals. This means no unconnected ports (except for when NUM_PORTS is 1).

3. You start your iteration on the first (least significant) unused port.

 

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Xilinx Employee
Xilinx Employee
4,089 Views
Registered: ‎08-01-2008

Re: Not able to generate hw platform

check these fourm posts as well
https://forums.xilinx.com/t5/Synthesis/WARNING-Xst-2677-and-explicitly-unconnected-ports-in-Verilog/td-p/189082

https://forums.xilinx.com/t5/Implementation/Leave-top-level-ports-unplaced/td-p/670336
Thanks and Regards
Balkrishan
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