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Observer imranashraf
Observer
7,029 Views
Registered: ‎06-01-2016

SDSoC Cycle Estimates with zero_copy

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For a kernel in my application, SDSoC estimates the number of cycles to be about 6M cycles. When I generate the hardware and test it on zedboard, the actual cycles are about 76M cycles. Most of the time, SDSoC estimates are quite reansoble, but in this case I was surprised. My doubt (which I want to clarify) is on the data copy. Does SDSoC includes the cycles to copy the data in and out of the accelerator into account?

 

I am using zero_copy to share the input and output buffer with the PL. So will SDSoC also take into account the data flush time (because of cf_wait calls generated in stub files) at the end of accelrator execution? I think not because this probably is the reason for such a large number of cycles.

 

If the answer to previous question is No, then how can this be estimated?

 

Furthermore, is it possible to tell SDSoC to not sync the input at it will not be modified by PL?

 

 

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Newbie yogeshc
Newbie
13,343 Views
Registered: ‎06-13-2016

Re: SDSoC Cycle Estimates with zero_copy

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Presently the performance estimation does not consider the time required to invalidate the cache. Estimation will be enhanced in a future release to do this.

 

If an argument is sent to the PL, or received from the PL, then SDSoC will generate the appropriate flush/invalidate for these arguments. If the data being passed is allocated with sds_alloc_non_cacheable(), then SDSoC will not flush/invalidate it if it is involved in transfers with the PL.

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Newbie yogeshc
Newbie
13,344 Views
Registered: ‎06-13-2016

Re: SDSoC Cycle Estimates with zero_copy

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Presently the performance estimation does not consider the time required to invalidate the cache. Estimation will be enhanced in a future release to do this.

 

If an argument is sent to the PL, or received from the PL, then SDSoC will generate the appropriate flush/invalidate for these arguments. If the data being passed is allocated with sds_alloc_non_cacheable(), then SDSoC will not flush/invalidate it if it is involved in transfers with the PL.

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Observer wsun
Observer
6,971 Views
Registered: ‎05-26-2016

Re: SDSoC Cycle Estimates with zero_copy

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For zero_copy, the performance estimation can be way off. The reason is as you have suspected: cache behavior. The zero_copy results in an AXI master interface INSIDE the HLS core, so the latency estimation from HLS scheduling already contains the zero_copy data transfer time, unfortunately, HLS cannot predict the cache behavior.

 

For non zero_copy data movers, such as AXI_DMA_SG, AXI_DMA_Simple, AXI_FIFO etc, the data transfer model contains the cache behavior, so the estimation can be more accurate.

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