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Explorer
Explorer
1,658 Views
Registered: ‎04-18-2017

SDSoC custom platform for ultrasclae AXI ports definition issues

Hello,

 

I am trying to create a custom platform for SDSoC following the UG1236 (SDSoC and Vivado 2017.4).

 

My design is this:

 

Screenshot from 2018-06-27 13-15-05.png

 

I found this thread where he builds a custom platform with an ultrascale, so I use his commands as reference:

 

set pfm [sdsoc::create_pfm design_1.hpfm]
sdsoc::pfm_name $pfm "TULIPP" "design_1" "design_1" "1.0"

sdsoc::pfm_clock $pfm pl_clk0 zynq_ultra_ps_e_0 0 true proc_sys_reset_0
sdsoc::pfm_clock $pfm pl_clk1 zynq_ultra_ps_e_0 1 false proc_sys_reset_1

sdsoc::pfm_axi_port $pfm M_AXI_HPM0_FPD zynq_ultra_ps_e_0 M_AXI_GP
sdsoc::pfm_axi_port $pfm M_AXI_HPM1_FPD zynq_ultra_ps_e_0 M_AXI_GP
sdsoc::pfm_axi_port $pfm M_AXI_HPM0_LPD zynq_ultra_ps_e_0 M_AXI_GP

sdsoc::pfm_axi_port $pfm S_AXI_HPC0_FPD zynq_ultra_ps_e_0 S_AXI_HPC
sdsoc::pfm_axi_port $pfm S_AXI_HPC1_FPD zynq_ultra_ps_e_0 S_AXI_HPC
sdsoc::pfm_axi_port $pfm S_AXI_HP0_FPD  zynq_ultra_ps_e_0 S_AXI_HP
sdsoc::pfm_axi_port $pfm S_AXI_HP1_FPD  zynq_ultra_ps_e_0 S_AXI_HP
sdsoc::pfm_axi_port $pfm S_AXI_HP2_FPD  zynq_ultra_ps_e_0 S_AXI_HP
sdsoc::pfm_axi_port $pfm S_AXI_HP3_FPD  zynq_ultra_ps_e_0 S_AXI_HP

for {set i 0} {$i < 8} {incr i} {
  sdsoc::pfm_irq $pfm In$i xlconcat_0
}

sdsoc::generate_hw_pfm $pfm

Then I export the hardware, generate the output products and create the hdl wrapper. Afterwards, I have to write the dsa file and I get the following errors:

 

write_dsa -force /home/ariel/Documents/TULIPP/SDSoC/platforms/emc2_ultra/design_1.dsa
INFO: [Vivado 12-4895] Creating DSA: /home/ariel/Documents/TULIPP/SDSoC/platforms/emc2_ultra/design_1.dsa ...
CRITICAL WARNING: [Project 1-655] Project does not have Board Part set. Board related data may be missing or incomplete in the generated DSA.
WARNING: [Project 1-646] Board name, vendor and part not set in DSA.
WARNING: [Project 1-645] Board images not set in DSA.
ERROR: [SDSoC-pfm-15] ERROR: sdsoc::pfm_axi_port - invalid port 'M_AXI_GP0' on instance 'zynq_ultra_ps_e_0'. Only ports on a processing_system7, zynq_ultra_ps_e, axi_interconnect, smartconnect and xlconcat blocks can be made available to SDSoC.
ERROR: [SDSoC-pfm-15] ERROR: sdsoc::pfm_axi_port - invalid port 'M_AXI_GP1' on instance 'zynq_ultra_ps_e_0'. Only ports on a processing_system7, zynq_ultra_ps_e, axi_interconnect, smartconnect and xlconcat blocks can be made available to SDSoC.
ERROR: [SDSoC-pfm-15] ERROR: sdsoc::pfm_axi_port - invalid port 'S_AXI_ACP' on instance 'zynq_ultra_ps_e_0'. Only ports on a processing_system7, zynq_ultra_ps_e, axi_interconnect, smartconnect and xlconcat blocks can be made available to SDSoC.
ERROR: [SDSoC-pfm-15] ERROR: sdsoc::pfm_axi_port - invalid port 'S_AXI_HP0' on instance 'zynq_ultra_ps_e_0'. Only ports on a processing_system7, zynq_ultra_ps_e, axi_interconnect, smartconnect and xlconcat blocks can be made available to SDSoC.
ERROR: [SDSoC-pfm-15] ERROR: sdsoc::pfm_axi_port - invalid port 'S_AXI_HP1' on instance 'zynq_ultra_ps_e_0'. Only ports on a processing_system7, zynq_ultra_ps_e, axi_interconnect, smartconnect and xlconcat blocks can be made available to SDSoC.
ERROR: [SDSoC-pfm-15] ERROR: sdsoc::pfm_axi_port - invalid port 'S_AXI_HP2' on instance 'zynq_ultra_ps_e_0'. Only ports on a processing_system7, zynq_ultra_ps_e, axi_interconnect, smartconnect and xlconcat blocks can be made available to SDSoC.
ERROR: [SDSoC-pfm-15] ERROR: sdsoc::pfm_axi_port - invalid port 'S_AXI_HP3' on instance 'zynq_ultra_ps_e_0'. Only ports on a processing_system7, zynq_ultra_ps_e, axi_interconnect, smartconnect and xlconcat blocks can be made available to SDSoC.
ERROR: [SDSoC-pfm-15] ERROR: sdsoc::pfm_irq - invalid port 'In8' on instance 'xlconcat_0'. Only ports on a processing_system7, zynq_ultra_ps_e, axi_interconnect, smartconnect and xlconcat blocks can be made available to SDSoC.
ERROR: [SDSoC-pfm-15] ERROR: sdsoc::pfm_irq - invalid port 'In9' on instance 'xlconcat_0'. Only ports on a processing_system7, zynq_ultra_ps_e, axi_interconnect, smartconnect and xlconcat blocks can be made available to SDSoC.
ERROR: [SDSoC-pfm-15] ERROR: sdsoc::pfm_irq - invalid port 'In10' on instance 'xlconcat_0'. Only ports on a processing_system7, zynq_ultra_ps_e, axi_interconnect, smartconnect and xlconcat blocks can be made available to SDSoC.
ERROR: [SDSoC-pfm-15] ERROR: sdsoc::pfm_irq - invalid port 'In11' on instance 'xlconcat_0'. Only ports on a processing_system7, zynq_ultra_ps_e, axi_interconnect, smartconnect and xlconcat blocks can be made available to SDSoC.
ERROR: [SDSoC-pfm-15] ERROR: sdsoc::pfm_irq - invalid port 'In12' on instance 'xlconcat_0'. Only ports on a processing_system7, zynq_ultra_ps_e, axi_interconnect, smartconnect and xlconcat blocks can be made available to SDSoC.
ERROR: [SDSoC-pfm-15] ERROR: sdsoc::pfm_irq - invalid port 'In13' on instance 'xlconcat_0'. Only ports on a processing_system7, zynq_ultra_ps_e, axi_interconnect, smartconnect and xlconcat blocks can be made available to SDSoC.
ERROR: [SDSoC-pfm-15] ERROR: sdsoc::pfm_irq - invalid port 'In14' on instance 'xlconcat_0'. Only ports on a processing_system7, zynq_ultra_ps_e, axi_interconnect, smartconnect and xlconcat blocks can be made available to SDSoC.
ERROR: [SDSoC-pfm-15] ERROR: sdsoc::pfm_irq - invalid port 'In15' on instance 'xlconcat_0'. Only ports on a processing_system7, zynq_ultra_ps_e, axi_interconnect, smartconnect and xlconcat blocks can be made available to SDSoC.
INFO: [Vivado 12-5881] Successfully generated hpfm file

Also, why do I get the first to errors if I am defining that with my first two lines, right?

 

Thank you for any help.

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12 Replies
Moderator
Moderator
1,645 Views
Registered: ‎09-12-2007

Re: SDSoC custom platform for ultrasclae AXI ports definition issues

Are you sourcing the pfm.tcl file?

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Explorer
Explorer
1,642 Views
Registered: ‎04-18-2017

Re: SDSoC custom platform for ultrasclae AXI ports definition issues

@stephenm,

 

I might be missing something in the UG1233 because it does not say anything about sourcing that file.

 

If I remember correctly, wasn't this in previous versions and it is deprecated on SDSoC 2017.4?

 

Thanks for the help.

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Moderator
Moderator
1,640 Views
Registered: ‎09-12-2007

Re: SDSoC custom platform for ultrasclae AXI ports definition issues

How are you setting the PFM? Are you calling these commands manually (ie one by one), or creating a script and calling them from here?

 

You can check that the PFM properties are set, by highlighting the zynq ultrascale IP in the BD and looking at the cell properties. In the CONFIG there should be PFM properties here.

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Explorer
Explorer
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Registered: ‎04-18-2017

Re: SDSoC custom platform for ultrasclae AXI ports definition issues

@stephenm,

 

I set the pfm at the beginning with

set pfm [sdsoc::create_pfm design_1.hpfm]

 

Yes I am calling these commands one by one manually to check if there are correct. I got no errors so I assume they are fine, that is why I tried to write the dsa file afterwards.

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Moderator
Moderator
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Registered: ‎09-12-2007

Re: SDSoC custom platform for ultrasclae AXI ports definition issues

I have been trying this on my end. My BD is similar to yours:

bd.PNG

 

I created a script with all my PFM properties based on the guide here:

https://www.xilinx.com/html_docs/xilinx2018_2/sdsoc_doc/zmt1517355484528.html

 

pfm_script.PNG

 

I have only added one slave port here. You can add all these if you wish as this will tell the SDx tool what interfaces are available.

To get the base names you can enable the interface in the ps wizard and view this in the address editor:

slaves.PNG

 

 

base_name.PNG

 

Here, I used a master IP (jtag to axi)just to show you.

 

Then just source the pfm.tcl, generate the output products and call the write_dsa command

 

tcl.PNG

 

 

 

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Explorer
Explorer
1,589 Views
Registered: ‎04-18-2017

Re: SDSoC custom platform for ultrasclae AXI ports definition issues

@stephenm,

 

Thank you very much for reproducing the workflow!

 

I followed your steps with your commands and now I have the .dsa, but I still get the following critical warnings:

 

 

write_dsa -force /home/ariel/Documents/TULIPP/SDSoC/platforms/emc2_ultra/emc2_ultra.dsa
INFO: [Vivado 12-4895] Creating DSA: /home/ariel/Documents/TULIPP/SDSoC/platforms/emc2_ultra/emc2_ultra.dsa ...
CRITICAL WARNING: [Project 1-655] Project does not have Board Part set. Board related data may be missing or incomplete in the generated DSA.
WARNING: [Project 1-646] Board name, vendor and part not set in DSA.
WARNING: [Project 1-645] Board images not set in DSA.
INFO: [Vivado 12-5881] Successfully generated hpfm file
INFO: [Vivado-projutils-8] Tcl script 'rebuild.tcl' generated in output directory '/home/ariel/.Xil/Vivado-14006-ariel-ESPRIMO-P957/dsa_2/prj'

INFO: [Vivado-projutils-17] Please note that the -paths_relative_to switch was specified, hence the project source files will be referenced wrt the
 path that was specified with this switch. The 'origin_dir' variable is set to '.' in the generated script.

WARNING: [Vivado-projutils-10] Found source(s) that were local or imported into the project. If this project is being source controlled, then
 please ensure that the project source(s) are also part of this source controlled data. The list of these local source(s) can be found in the generated script
 under the header section.

INFO: [Vivado 12-4896] Successfully created DSA: /home/ariel/Documents/TULIPP/SDSoC/platforms/emc2_ultra/emc2_ultra.dsa
write_dsa: Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 7198.938 ; gain = 16.312 ; free physical = 1923 ; free virtual = 7576
/home/ariel/Documents/TULIPP/SDSoC/platforms/emc2_ultra/emc2_ultra.dsa

 

  1. In the settings I chose a part rather than the board. Is that the reason I get the critical warning that the board part is not set?
  2. Why board name, vendor, part and image are not set? Aren't those done with set_property PFM_NAME "xilinx.com:my_plat:my_plat:1.0" [get_files *.bd]?
    1. Instead of my_plat I am writing the same name I give to the block design. Does it affect that?

Thank you for the help.

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Explorer
Explorer
1,585 Views
Registered: ‎04-18-2017

Re: SDSoC custom platform for ultrasclae AXI ports definition issues

Even though I got that critical warning, I went ahead with the tutorial to create a custom platform so I generated the linker, .bif and .bin files and followed the steps on SDx.

 

I have a working code (tested with the zcu 102 platform shipped with SDSoC) and when I built it, I got the following error:

 

Screenshot from 2018-06-27 19-23-06.png

 

The complete error:

ERROR: [SdsCompiler 83-5019] Exiting sds++ : Error when calling '/opt/Xilinx/SDSoC/SDx/2017.4/bin/sdx_link  -cf-system /home/ariel/Documents/sdsoc_prjts/emc2_ultra_test/Release/_sds/.llvm/apsys_0.xml  -cf-db  /home/ariel/Documents/sdsoc_prjts/emc2_ultra_test/Release/_sds/.cdb/xd_ip_db.xml  -xpfm /home/ariel/Documents/sdsoc_prjts/emc2_ultra/export/emc2_ultra/emc2_ultra.xpfm   -multi-clks -trace-buffer 1024 -quiet'

Thank you for the help.

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Explorer
Explorer
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Registered: ‎04-18-2017

Re: SDSoC custom platform for ultrasclae AXI ports definition issues

@stephenm,

 

I miss the tip from UG1146 "If the Vivado design project contains more than one block diagram, one block diagram must have the same name as the hardware platform, and that block diagram is used by the SDx platform project." so now the project and block design have the same name.

 

But still, when I user your commands but replacing my_plat with the name of the project and block design, I still get the same critical warning and the two following warnings shown before.

 

Thanks for the help again.

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Moderator
Moderator
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Registered: ‎09-12-2007

Re: SDSoC custom platform for ultrasclae AXI ports definition issues

The PFM name should be:

set_property PFM_NAME emc2_ultra [get_files *.bd]

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Explorer
Explorer
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Registered: ‎04-18-2017

Re: SDSoC custom platform for ultrasclae AXI ports definition issues

Which is what you do with set_property PFM_NAME "xilinx.com:my_plat:my_plat:1.0" [get_files *.bd], or not?

 

After having the same name for project and block design, I went through to generate the .dsa and create the SDSoC platform and now I have the same issue as this thread:

Preliminary link application ELF
/opt/Xilinx/SDSoC/SDx/2017.4/target/aarch64-none/lib/libsds_lib.a(sds_perf_instrumentation_standalone.o): In function `apf_perf_estimation_exit':
sds_perf_instrumentation_standalone.c:(.text+0x49c): undefined reference to `f_open'
sds_perf_instrumentation_standalone.c:(.text+0x4bc): undefined reference to `f_write'
sds_perf_instrumentation_standalone.c:(.text+0x4c4): undefined reference to `f_close'
collect2: error: ld returned 1 exit status
ERROR: [SdsCompiler 83-5019] Exiting sds++ : Error when calling 'aarch64-none-elf-g++ -Wl,--build-id=none -Wl,-T -Wl,/home/ariel/Documents/sdsoc_prjts/emc2_ultra/export/emc2_ultra/sw/standalone/standalone/lscript.ld /home/ariel/Documents/sdsoc_prjts/emc2_ultra_test/Release/_sds/est/sw_perf_est.o  /home/ariel/Documents/sdsoc_prjts/emc2_ultra_test/Release/_sds/est/main.o /home/ariel/Documents/sdsoc_prjts/emc2_ultra_test/Release/_sds/swstubs/portinfo.o  -L /home/ariel/Documents/sdsoc_prjts/emc2_ultra_test/Release/_sds/swstubs/standalone_bsp/psu_cortexa53_0/lib  -L /opt/Xilinx/SDSoC/SDx/2017.4/target/aarch64-none/lib -L/home/ariel/Documents/sdsoc_prjts/emc2_ultra_test/Release/_sds/swstubs -Wl,--start-group -lxilffs -lgcc -lc -lstdc++ -Wl,--end-group -Wl,--start-group   -lxilffs -lxil -lsds_link -lgcc -lc  -lsds_lib -lxlnk_stub -lgcc -lc -Wl,--end-group -o /home/ariel/Documents/sdsoc_prjts/emc2_ultra_test/Release/_sds/swstubs/emc2_ultra_test.elf'
sds++ log file saved as /home/ariel/Documents/sdsoc_prjts/emc2_ultra_test/Release/_sds/reports/sds.log
ERROR: [SdsCompiler 83-5004] Build failed

make: *** [emc2_ultra_test.elf] Error 1
makefile:45: recipe for target 'emc2_ultra_test.elf' failed

But when I check the Board Support Package in the platform project, it is empty:

Screenshot from 2018-06-28 14-29-51.png

 

I did not select xilffs in the BSP on SDK. Should I have done it even though I will not use an SD card?

 

Thanks for the help.

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Moderator
Moderator
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Registered: ‎09-12-2007

Re: SDSoC custom platform for ultrasclae AXI ports definition issues

If you are not generating the SD card, then you shouldn't need to do this. However, this is why it is failing (and it looks like a bug). I would just add this to the BSP and try again, as it would be quick to rectify.

 

Hopefully, you will get this working :-)

 

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Registered: ‎04-18-2017

Re: SDSoC custom platform for ultrasclae AXI ports definition issues

So I just added the xilffs to the BSP on SDK and generated there a new linker script. Then I removed the "old" platform and followed the steps to create a new one with the new linker.

The issue remains and in the BSP on SDSoC (image from previous post) does not show the BSP. I added it manually emc2_ultra.sdk/empty_application_bsp/system.mss to the Bsp Settings File but still nothing changed.
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