cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
leonardo_suriano
Participant
Participant
4,223 Views
Registered: ‎01-13-2017

creating SDSoC platform for Pynq Board

Following the instruction of the Xilinx's tutorial UG1236, I created a hardware platform for that board.

Also, I use the SW file for the board already tested and working perfectly.

Cases:

1 - creating a HelloWorld project, compiling it in SDSoC, running the application on Linux on pynq -> PERFECT

2 - running the matmul example just in software (NO HARDWARE FUNCTIONS) and running it on Linux on Pynq board -> PERFECT

3 - the problems come when I want to move the function on hardware:

  3.1 - for standalone application -> PERFECT

  3.2 - when compiling to execute on Linux, I have this ERROR MESSAGES:

 

 

INFO: [DMAnalysis 83-4494] Analyzing hardware accelerators...
WARNING: [DMAnalysis 83-1005] Invalid clock id 2 for platform pynq
INFO: [DMAnalysis 83-4497] Analyzing callers to hardware accelerators...
INFO: [DMAnalysis 83-4444] Scheduling data transfer graph for partition 0
WARNING: [DMAnalysis 83-1005] Invalid clock id 2 for platform pynq
ERROR: [DMAnalysis 83-4503] No M_AXI_GP port found in the platform!
ERROR: [DMAnalysis 83-4445] Failed scheduling data transfer graph!
XidanePass exited with return code 1
- errors detected

 

How to fix this problem? Ideas?

 

Also, a link to a working platform for Pynq board running linux is appreciated. Surfing on the web I have found other platform developed by all of them have the same problem.

 

 

 

 

 

 

 

0 Kudos
13 Replies
huyao4450
Visitor
Visitor
4,131 Views
Registered: ‎09-06-2015

I have got similar problem, have you found the cause?

0 Kudos
skalicky
Explorer
Explorer
4,126 Views
Registered: ‎09-19-2017

Hi Guys,

 

Heres two working Pynq platforms that ive made and use in my Python + HLS project: https://github.com/ISI-RCG/spicy/tree/master/platforms

 

The pynq_bare is similar to zc702 platform with nothing in it besides the clocks. 

 

The pynq_hdmi has the HDMI in/out paths connected via VDMAs to DDR.

 

These platforms are built with the 2017.4 version of SDSoC.

 

Sam

khareashish_trimble
Adventurer
Adventurer
4,115 Views
Registered: ‎10-17-2017

@skalicky This is great. I've been looking for a Pynq platform for a while.

Do you have any examples on how to use the HDMI in/out in the SDSOC project ? 

0 Kudos
skalicky
Explorer
Explorer
4,111 Views
Registered: ‎09-19-2017

Hi,

I havent been able to use the HDMI in/out from C/C++ yet. So far ive been running Python applications using Pynq's HDMI API to read/write frames. Then I send these frames from Python down to my SDSoC generated accelerator. Im using the SDSoC library flow to do this.

I havent uploaded any examples of this yet, still cleaning up my code. but i am hoping to upload these examples in the next week or two.

Its not impossible to use the HDMI in/out from C, someone just has to write some drivers to use the VDMAs that are in the platform. Thats probably a longer term solution, but something that I would like to do at some point.

Sam
0 Kudos
leonardo_suriano
Participant
Participant
4,103 Views
Registered: ‎01-13-2017

I am going to test it and I will give you feedback!

0 Kudos
huyao4450
Visitor
Visitor
4,089 Views
Registered: ‎09-06-2015

Thanks, but do you know why does that error happen?

 No M_AXI_GP port found

I am not using a  pynq board and want to create a custom platform, I tryed on zc702 and zcu102 both, when I was creating the platform there is no error, but when I try to compile sdsoc application project on the custom platform I build, this issue come out, could you help me?

0 Kudos
vandenplas
Visitor
Visitor
3,957 Views
Registered: ‎11-02-2017

I also get the same issue with a custom platform

 

ERROR: [DMAnalysis 83-4503] No M_AXI_GP port found in the platform!

ERROR: [DMAnalysis 83-4445] Failed scheduling data transfer graph!

 

Did you find the fix?

0 Kudos
leonardo_suriano
Participant
Participant
3,568 Views
Registered: ‎01-13-2017

nope! I think that Xilinx should answer
0 Kudos
gill
Xilinx Employee
Xilinx Employee
3,455 Views
Registered: ‎05-23-2016

While this error is where the tool is halting, you very likely saw some suspicious messages related to clock ID prior to the reported error.  Things like this:

WARNING: [DMAnalysis 83-1005] Invalid clock id 1 for platform XYZ

 

Typically this is the result of a naming mismatch between the platform and the platform's content.  You can encounter this if the platform directory has been renamed, or if the .dsa file internal to the platform has been renamed or was incorrectly exported.  Unfortunately, names are important, and at least today renaming causes mismatches down-stream.

 

Also, thanks Skalicky for contributions.

bluetiger9
Adventurer
Adventurer
2,725 Views
Registered: ‎09-02-2018

@gill, can you explain this in more details please?

I have a similar problem with the custom platform I'm trying to create for an Ultra96 board:

 

...
Generating data motion network INFO: [DMAnalysis 83-4494] Analyzing hardware accelerators... WARNING: [DMAnalysis 83-10051] Invalid clock id 2 for platform ultra96_board WARNING: [DMAnalysis 83-10051] Invalid clock id 2 for platform ultra96_board WARNING: [DMAnalysis 83-10051] Invalid clock id 2 for platform ultra96_board INFO: [DMAnalysis 83-4497] Analyzing callers to hardware accelerators... INFO: [DMAnalysis 83-4444] Scheduling data transfer graph for partition 0 WARNING: [DMAnalysis 83-10051] Invalid clock id 2 for platform ultra96_board ERROR: [DMAnalysis 83-4503] No M_AXI_GP port found in the platform! ERROR: [DMAnalysis 83-4445] Failed scheduling data transfer graph! Data motion generation exited with return code 1 - errors detected sds++ log file saved as /home/bluetiger/dev/XIlinx/SDx/test/Debug/_sds/reports/sds.log ERROR: [SdsCompiler 83-5004] Build failed make: *** [test.elf] Error 1 makefile:45: recipe for target 'test.elf' failed 20:51:31 Build Finished (took 2m:29s.653ms)

 


It's weird because both the clock with id=2 and ports M_AXI_GP are defined in the DSA.

Vivado / SDK / SDx version: 2018.2


I uploaded the generated DSA in my Dropbox:

https://www.dropbox.com/s/jlggj7nwadjfw44/ultra96_board.dsa?dl=0

Here you can found more info about what I try to achieve:
https://xilinx2018.hackster.io/t/xilinx-revision-support-on-ultra96/870

 

Can you take a look?

 

Thanks,

Attila

0 Kudos
bluetiger9
Adventurer
Adventurer
2,720 Views
Registered: ‎09-02-2018

No way!

 

It was the .dsa file / SDx Platform Project name. Apparently, booth needs to be the same as the name from the PFM_NAME...

 

PFM_NAME = em.avnet.com:ultra96:ultra96:1.2

DSA / Platform Project name = ultra96_board.dsa / ultra96_board
   ===> Weird Error!

DSA / Platform Project name = ultra96.dsa / ultra96
   ===> OK!

Makes lot of sense...

XILINX: It would worth showing an error / warning in Vivado / SDx, when trying to use incorrect names.

 

 

mcggoal
Contributor
Contributor
2,561 Views
Registered: ‎08-02-2016

great job!  It is such a big trap for our beginners....

0 Kudos
khareashish_trimble
Adventurer
Adventurer
1,685 Views
Registered: ‎10-17-2017

Thanks @bluetiger9

I was running into a similar issue for a custom hardware platform for ZCU102. 

Certainly looks like SDSoC does not like it when   the .dsa file / SDx Platform Project name are different. 

 

0 Kudos