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Adventurer
Adventurer
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Registered: ‎12-16-2013

document of adapter_v3_0 (Beta) generated by SDSoC?

Hi all,

When we use SDSoC to implement a hardware accelerator such this simple adder

void adder (float A[1024], float B[1024], float C[1024]) {
  for (int i = 0; i < 1024; i++) {
#pragma HLS PIPELINE
    C[i] = A[i] + B[i];
  }
}

In the generated vivado project, the SDSoC tool adds an instance of an IP called "adapter_v3_0 (Beta)" as an interface that connects the accelerator to the rest of system.

adapter_v3_0,png.png

This interface provides an interrupt signal called app_done_irq. I am going to use this interrupt in my system.
I couldn't find any document about this IP and registers behind the interrupt signal.


I am wondering if somebody knows the registers inside this IP (their offset address and content), especially interrupt control and status registers that I can use the interrupt in my design in Linux. (yes, with the help of a piece of Linux device driver).

 

Thanks

Mohammad

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